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      1 //===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This implements routines for translating functions from LLVM IR into
     11 // Machine IR.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     16 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     17 
     18 #include "llvm/ADT/APInt.h"
     19 #include "llvm/ADT/DenseMap.h"
     20 #include "llvm/ADT/IndexedMap.h"
     21 #include "llvm/ADT/SmallPtrSet.h"
     22 #include "llvm/ADT/SmallVector.h"
     23 #include "llvm/CodeGen/MachineBasicBlock.h"
     24 #include "llvm/CodeGen/ValueTypes.h"
     25 #include "llvm/IR/InlineAsm.h"
     26 #include "llvm/IR/Instructions.h"
     27 #include "llvm/Target/TargetRegisterInfo.h"
     28 #include <vector>
     29 
     30 namespace llvm {
     31 
     32 class AllocaInst;
     33 class BasicBlock;
     34 class BranchProbabilityInfo;
     35 class CallInst;
     36 class Function;
     37 class GlobalVariable;
     38 class Instruction;
     39 class MachineInstr;
     40 class MachineBasicBlock;
     41 class MachineFunction;
     42 class MachineModuleInfo;
     43 class MachineRegisterInfo;
     44 class TargetLowering;
     45 class Value;
     46 
     47 //===--------------------------------------------------------------------===//
     48 /// FunctionLoweringInfo - This contains information that is global to a
     49 /// function that is used when lowering a region of the function.
     50 ///
     51 class FunctionLoweringInfo {
     52   const TargetMachine &TM;
     53 public:
     54   const Function *Fn;
     55   MachineFunction *MF;
     56   MachineRegisterInfo *RegInfo;
     57   BranchProbabilityInfo *BPI;
     58   /// CanLowerReturn - true iff the function's return value can be lowered to
     59   /// registers.
     60   bool CanLowerReturn;
     61 
     62   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
     63   /// allocated to hold a pointer to the hidden sret parameter.
     64   unsigned DemoteRegister;
     65 
     66   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
     67   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
     68 
     69   /// ValueMap - Since we emit code for the function a basic block at a time,
     70   /// we must remember which virtual registers hold the values for
     71   /// cross-basic-block values.
     72   DenseMap<const Value*, unsigned> ValueMap;
     73 
     74   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
     75   /// the entry block.  This allows the allocas to be efficiently referenced
     76   /// anywhere in the function.
     77   DenseMap<const AllocaInst*, int> StaticAllocaMap;
     78 
     79   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
     80   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
     81 
     82   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
     83   /// function arguments that are inserted after scheduling is completed.
     84   SmallVector<MachineInstr*, 8> ArgDbgValues;
     85 
     86   /// RegFixups - Registers which need to be replaced after isel is done.
     87   DenseMap<unsigned, unsigned> RegFixups;
     88 
     89   /// MBB - The current block.
     90   MachineBasicBlock *MBB;
     91 
     92   /// MBB - The current insert position inside the current block.
     93   MachineBasicBlock::iterator InsertPt;
     94 
     95 #ifndef NDEBUG
     96   SmallPtrSet<const Instruction *, 8> CatchInfoLost;
     97   SmallPtrSet<const Instruction *, 8> CatchInfoFound;
     98 #endif
     99 
    100   struct LiveOutInfo {
    101     unsigned NumSignBits : 31;
    102     bool IsValid : 1;
    103     APInt KnownOne, KnownZero;
    104     LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
    105                     KnownZero(1, 0) {}
    106   };
    107 
    108   /// VisitedBBs - The set of basic blocks visited thus far by instruction
    109   /// selection.
    110   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
    111 
    112   /// PHINodesToUpdate - A list of phi instructions whose operand list will
    113   /// be updated after processing the current basic block.
    114   /// TODO: This isn't per-function state, it's per-basic-block state. But
    115   /// there's no other convenient place for it to live right now.
    116   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
    117 
    118   /// If the current MBB is a landing pad, the exception pointer and exception
    119   /// selector registers are copied into these virtual registers by
    120   /// SelectionDAGISel::PrepareEHLandingPad().
    121   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
    122 
    123   explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
    124 
    125   /// set - Initialize this FunctionLoweringInfo with the given Function
    126   /// and its associated MachineFunction.
    127   ///
    128   void set(const Function &Fn, MachineFunction &MF);
    129 
    130   /// clear - Clear out all the function-specific state. This returns this
    131   /// FunctionLoweringInfo to an empty state, ready to be used for a
    132   /// different function.
    133   void clear();
    134 
    135   /// isExportedInst - Return true if the specified value is an instruction
    136   /// exported from its block.
    137   bool isExportedInst(const Value *V) {
    138     return ValueMap.count(V);
    139   }
    140 
    141   unsigned CreateReg(MVT VT);
    142 
    143   unsigned CreateRegs(Type *Ty);
    144 
    145   unsigned InitializeRegForValue(const Value *V) {
    146     unsigned &R = ValueMap[V];
    147     assert(R == 0 && "Already initialized this value register!");
    148     return R = CreateRegs(V->getType());
    149   }
    150 
    151   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    152   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
    153   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
    154     if (!LiveOutRegInfo.inBounds(Reg))
    155       return NULL;
    156 
    157     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
    158     if (!LOI->IsValid)
    159       return NULL;
    160 
    161     return LOI;
    162   }
    163 
    164   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    165   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
    166   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
    167   /// the larger bit width by zero extension. The bit width must be no smaller
    168   /// than the LiveOutInfo's existing bit width.
    169   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
    170 
    171   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
    172   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
    173                          const APInt &KnownZero, const APInt &KnownOne) {
    174     // Only install this information if it tells us something.
    175     if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
    176       return;
    177 
    178     LiveOutRegInfo.grow(Reg);
    179     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
    180     LOI.NumSignBits = NumSignBits;
    181     LOI.KnownOne = KnownOne;
    182     LOI.KnownZero = KnownZero;
    183   }
    184 
    185   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
    186   /// register based on the LiveOutInfo of its operands.
    187   void ComputePHILiveOutRegInfo(const PHINode*);
    188 
    189   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
    190   /// called when a block is visited before all of its predecessors.
    191   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
    192     // PHIs with no uses have no ValueMap entry.
    193     DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
    194     if (It == ValueMap.end())
    195       return;
    196 
    197     unsigned Reg = It->second;
    198     LiveOutRegInfo.grow(Reg);
    199     LiveOutRegInfo[Reg].IsValid = false;
    200   }
    201 
    202   /// setArgumentFrameIndex - Record frame index for the byval
    203   /// argument.
    204   void setArgumentFrameIndex(const Argument *A, int FI);
    205 
    206   /// getArgumentFrameIndex - Get frame index for the byval argument.
    207   int getArgumentFrameIndex(const Argument *A);
    208 
    209 private:
    210   /// LiveOutRegInfo - Information about live out vregs.
    211   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
    212 };
    213 
    214 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
    215 /// being passed to this variadic function, and set the MachineModuleInfo's
    216 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
    217 /// reference to _fltused on Windows, which will link in MSVCRT's
    218 /// floating-point support.
    219 void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);
    220 
    221 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
    222 /// call, and add them to the specified machine basic block.
    223 void AddCatchInfo(const CallInst &I,
    224                   MachineModuleInfo *MMI, MachineBasicBlock *MBB);
    225 
    226 /// AddLandingPadInfo - Extract the exception handling information from the
    227 /// landingpad instruction and add them to the specified machine module info.
    228 void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
    229                        MachineBasicBlock *MBB);
    230 
    231 } // end namespace llvm
    232 
    233 #endif
    234