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  /external/llvm/lib/CodeGen/
PHIEliminationUtils.cpp 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg),
38 RE = MRI.reg_end(); RI != RE; ++RI) {
CriticalAntiDepBreaker.h 36 MachineRegisterInfo &MRI;
RegAllocBase.h 62 MachineRegisterInfo *MRI;
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
DeadMachineInstructionElim.cpp 33 const MachineRegisterInfo *MRI;
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
88 MRI = &MF.getRegInfo();
100 LivePhysRegs = MRI->getReservedRegs();
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
132 E = MRI->use_end(); I!=E; I=nextI) {
ProcessImplicitDefs.cpp 30 MachineRegisterInfo *MRI;
84 MRI->use_nodbg_begin(Reg),
85 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
146 MRI = &MF.getRegInfo();
147 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
AggressiveAntiDepBreaker.h 119 MachineRegisterInfo &MRI;
LLVMTargetMachine.cpp 165 const MCRegisterInfo &MRI = *getRegisterInfo();
174 MII, MRI, STI);
180 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
198 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
270 const MCRegisterInfo &MRI = *getRegisterInfo();
272 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
LiveRangeCalc.h 38 const MachineRegisterInfo *MRI;
130 LiveRangeCalc() : MF(0), MRI(0), Indexes(0), DomTree(0), Alloc(0) {}
OptimizePHIs.cpp 31 MachineRegisterInfo *MRI;
64 MRI = &Fn.getRegInfo();
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
143 E = MRI->use_end(); I != E; ++I) {
168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
171 MRI->replaceRegWith(OldReg, SingleValReg);
UnreachableBlockElim.cpp 200 MachineRegisterInfo &MRI = F.getRegInfo();
201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
202 MRI.replaceRegWith(Output, Input);
  /external/llvm/include/llvm/CodeGen/
MachineSSAUpdater.h 55 MachineRegisterInfo *MRI;
FastISel.h 51 MachineRegisterInfo &MRI;
LiveRegMatrix.h 42 MachineRegisterInfo *MRI;
LiveVariables.h 111 MachineRegisterInfo &MRI);
130 MachineRegisterInfo* MRI;
282 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
  /external/llvm/lib/Target/NVPTX/
NVPTXFrameLowering.cpp 40 MachineRegisterInfo &MRI = MF.getRegInfo();
45 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
52 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
NVPTXInstrInfo.cpp 35 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
36 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
37 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.h 31 MachineRegisterInfo *MRI;
  /external/llvm/lib/Target/R600/
SIFixSGPRCopies.cpp 83 const MachineRegisterInfo &MRI,
110 const MachineRegisterInfo &MRI,
117 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
118 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
119 E = MRI.use_end(); I != E; ++I) {
122 RC = TRI->getCommonSubClass(RC, inferRegClass(TRI, MRI,
132 MachineRegisterInfo &MRI = MF.getRegInfo();
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
147 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
SIAssignInterpRegs.cpp 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
SIAssignInterpRegs.cpp 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
    [all...]
  /external/llvm/include/llvm/MC/
MCInstPrinter.h 41 const MCRegisterInfo &MRI;
59 const MCRegisterInfo &mri)
60 : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 48 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
49 if (!MRI)
53 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
70 MCContext *Ctx = new MCContext(MAI, MRI, 0);
93 *MAI, *MII, *MRI, *STI);
99 TheTarget, MAI, MRI,
224 const MCRegisterInfo *MRI = DC->getRegisterInfo();
229 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
  /external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 154 MachineRegisterInfo *MRI = &MF.getRegInfo();
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
195 MachineRegisterInfo *MRI = &MF.getRegInfo();
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
  /external/llvm/lib/Target/Mips/
Mips16FrameLowering.cpp 43 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
59 unsigned S2 = MRI->getDwarfRegNum(Mips::S2, true);
62 unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
65 unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
68 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
  /external/llvm/lib/Target/R600/MCTargetDesc/
SIMCCodeEmitter.cpp 41 const MCRegisterInfo &MRI;
50 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
52 : MCII(mcii), MRI(mri) { }
68 const MCRegisterInfo &MRI,
71 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
173 return MRI.getEncodingValue(MO.getReg());

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