| /external/chromium_org/third_party/leveldatabase/src/util/ |
| crc32c.h | 31 inline uint32_t Mask(uint32_t crc) {
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/reference/vc/m4p10/src/ |
| omxVCM4P10_GetVLCInfo.c | 72 OMX_U32 Mask = 4, RunBefore;
129 Value == -1 ? Mask : 0;
130 Mask >>= 1;
136 Mask = 0;
147 /* Mask becomes zero after entering */
148 if (Mask &&
155 Value == -1 ? Mask : 0;
156 Mask >>= 1;
163 if (Mask)
165 Mask = 0
[all...] |
| /external/clang/include/clang/AST/ |
| DeclAccessPair.h | 33 enum { Mask = 0x3 };
43 return (NamedDecl*) (~Mask & (uintptr_t) Ptr);
46 return AccessSpecifier(Mask & (uintptr_t) Ptr);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 81 unsigned Mask = MBBI->getOperand(1).getImm();
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
573 unsigned Mask = (1 << NumBits) - 1;
574 if ((unsigned)Offset <= Mask * Scale) {
590 ImmedOffset = ImmedOffset & Mask;
603 Offset &= ~(Mask*Scale);
|
| Thumb1RegisterInfo.cpp | 384 unsigned Mask = (1 << NumBits) - 1;
385 if (((Offset / Scale) & ~Mask) == 0) {
418 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
421 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
423 Offset = (Offset - Mask * Scale);
453 unsigned Mask = (1 << NumBits) - 1;
455 if ((unsigned)Offset <= Mask * Scale) {
470 Mask = (1 << NumBits) - 1;
478 ImmedOffset = ImmedOffset & Mask;
480 Offset &= ~(Mask * Scale)
[all...] |
| Thumb2ITBlockPass.cpp | 194 unsigned Mask = 0, Pos = 3;
208 Mask |= (NCC & 1) << Pos;
228 // Finalize IT mask.
229 Mask |= (1 << Pos);
230 // Tag along (firstcond[0] << 4) with the mask.
231 Mask |= (CC & 1) << 4;
232 MIB.addImm(Mask);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 138 uint64_t Mask = ((uint64_t)(-1) >>
140 CurVal |= Value & Mask;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 92 int64_t Mask = 0xffff;
94 Offset = OldOffset & Mask;
96 Mask >>= 1;
97 assert(Mask && "One offset must be OK");
|
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | 89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
90 unsigned Mask;
100 LiveBundle() : Mask(0), FixCount(0) {}
103 bool isFixed() const { return !Mask || FixCount; }
115 unsigned Mask = 0;
121 Mask |= 1 << (Reg - X86::FP0);
123 return Mask;
296 /// Adjust the live registers to be the set in Mask.
297 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
397 const unsigned Mask = calcLiveInMask(MBB)
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/ |
| Xdefs.h | 75 typedef unsigned long Mask;
77 typedef CARD32 Mask;
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xdefs.h | 75 typedef unsigned long Mask;
77 typedef CARD32 Mask;
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xdefs.h | 75 typedef unsigned long Mask;
77 typedef CARD32 Mask;
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 84 static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) {
85 for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
86 if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
208 SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
210 if (NumVecElems == Mask.size() && isReverseVectorMask(Mask))
|
| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 179 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
187 if (Mask) {
271 bool Mask = false;
277 // Mask the write if the original instruction does not write to
279 Mask = (Chan != TRI.getHWRegChan(DstReg));
305 if (Mask) {
|
| R600TextureIntrinsicsReplacer.cpp | 126 Constant *Mask[] = {
132 Value *SwizzleMask = ConstantVector::get(Mask);
|
| /external/llvm/include/llvm/ADT/ |
| BitVector.h | 181 // Mask off previous bits.
257 BitWord Mask = EMask - IMask;
258 Bits[I / BITWORD_SIZE] |= Mask;
295 BitWord Mask = EMask - IMask;
296 Bits[I / BITWORD_SIZE] &= ~Mask;
333 BitWord Mask = 1L << (Idx % BITWORD_SIZE);
334 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
484 // Portable bit mask operations.
492 // bit mask is always a whole multiple of 32 bits. If no bit mask size i
[all...] |
| SmallBitVector.h | 232 // Mask off previous bits.
311 uintptr_t Mask = EMask - IMask;
312 setSmallBits(getSmallBits() | Mask);
342 uintptr_t Mask = EMask - IMask;
343 setSmallBits(getSmallBits() & ~Mask);
523 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
524 /// This computes "*this |= Mask".
525 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
527 applyMask<true, false>(Mask, MaskWords);
529 getPointer()->setBitsInMask(Mask, MaskWords)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 165 unsigned Mask = BundledPred | BundledSucc;
166 Flags = (Flags & Mask) | (flags & ~Mask);
784 /// This may also return a register mask operand when Overlap is true.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 47 unsigned Mask = MI.getOperand(1).getImm();
50 if (Mask & 1)
53 if (Mask & 2)
56 if (Mask & 4)
59 if (Mask & 8)
62 if (Mask & 16)
65 if (Mask & 32)
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| bitstream_io.cpp | 29 static const UChar Mask[ ] =
372 BitstreamPutBits(stream, restBits, Mask[restBits]);
400 BitstreamPutBits(stream,count,Mask[count]);
|
| /external/chromium_org/chromeos/network/onc/ |
| onc_utils.cc | 243 static scoped_ptr<base::DictionaryValue> Mask(
246 const std::string& mask) {
247 OncMaskValues masker(mask);
253 explicit OncMaskValues(const std::string& mask)
254 : mask_(mask) {
271 // Mask to insert in place of the sensitive values.
280 const std::string& mask) {
281 return OncMaskValues::Mask(signature, onc_object, mask);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 40 unsigned int Mask;
113 && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
128 unsigned int mask)
134 sc_data.Mask = mask;
674 unsigned int mask)
677 if (rc_src_reads_dst_mask(file, mask, index,
689 unsigned int mask)
693 (mask & d->Writer->WriteMask)) {
|
| /external/llvm/include/llvm/Support/ |
| MathExtras.h | 59 T Mask = std::numeric_limits<T>::max() >> Shift;
61 if ((Val & Mask) == 0) {
66 Mask >>= Shift;
|
| /external/llvm/lib/IR/ |
| Attributes.cpp | 486 uint64_t Mask = 0;
498 Mask |= (Log2_32(ASN->getAlignment()) + 1) << 16;
500 Mask |= (Log2_32(ASN->getStackAlignment()) + 1) << 26;
502 Mask |= AttributeImpl::getAttrMask(Kind);
505 return Mask;
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 479 uint64_t Mask = 0;
484 Mask |= (uint64_t)0xff << (8 * ByteNum);
488 O.write_hex(Mask);
|
