/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 299 MachineOperand Op2 = MI->getOperand(S2); 300 ChangeOpInto(MI->getOperand(S1), Op2);
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HexagonHardwareLoops.cpp | 524 const MachineOperand &Op2 = CondI->getOperand(2); 528 if (Op2.isImm() || Op1.getReg() == IVReg) 529 EndValue = &Op2; [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 358 unsigned Op1, Op2; 359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 371 unsigned Op1, Op2; 372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 377 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder) [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.cpp | 776 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits 786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 791 Ops[4].getAsInteger(10, Op2); 792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 818 uint32_t Op2 = Bits & 0x7; 831 + "_c" + utostr(CRm) + "_" + utostr(Op2); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 581 SDValue Op2 = Op.getOperand(2); 584 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 659 SDValue Op2 = Op.getOperand(2); 687 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
LegalizeIntegerTypes.cpp | 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 185 Op2, N->getMemOperand(), N->getOrdering(), 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), [all...] |
LegalizeVectorTypes.cpp | 138 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); 140 Op0.getValueType(), Op0, Op1, Op2); [all...] |
SelectionDAGBuilder.cpp | [all...] |
/external/llvm/lib/Bitcode/Reader/ |
BitcodeReader.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
RegisterCoalescer.cpp | 605 unsigned Op1, Op2, NewDstIdx; 606 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 609 NewDstIdx = Op2; 610 else if (Op2 == UseOpIdx) [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | [all...] |
X86ISelDAGToDAG.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineCompares.cpp | [all...] |
/frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
BitcodeReader.cpp | [all...] |
/frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
BitcodeReader.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | 118 unsigned Op2, bool Op2IsKill); 348 unsigned Op2, bool Op2IsKill) { 356 .addReg(Op2, Op2IsKill * RegState::Kill)); 361 .addReg(Op2, Op2IsKill * RegState::Kill)); [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 152 ICToken Op2 = OperandStack.pop_back_val(); 159 Val = Op1.second + Op2.second; 163 Val = Op1.second - Op2.second; 167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 169 Val = Op1.second * Op2.second; 173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 175 assert (Op2.second != 0 && "Division by zero!"); 176 Val = Op1.second / Op2.second; [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |