| /external/chromium_org/third_party/icu/source/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
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| /external/chromium_org/skia/ext/ |
| recursive_gaussian_convolution.h | 21 enum Order {
29 SK_API RecursiveFilter(float sigma, Order order);
31 Order order() const { return order_; } function in class:skia::RecursiveFilter
35 Order order_;
|
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
30 ArrayRef<MCPhysReg> Order;
42 /// Get the allocation order without reordered hints.
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
45 /// Return the next physical register in the allocation order, or 0.
51 while (Pos < int(Order.size())) {
52 unsigned Reg = Order[Pos++];
60 /// Limit'th register in the RegisterClassInfo allocation order
[all...] |
| TargetRegisterInfo.cpp | 125 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
126 for (unsigned i = 0; i != Order.size(); ++i)
127 R.set(Order[i]);
257 ArrayRef<MCPhysReg> Order,
279 // Check that Phys is in the allocation order. We shouldn't heed hints
280 // from VirtReg's register class if they aren't in the allocation order. The
282 if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
|
| CriticalAntiDepBreaker.cpp | 366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
367 for (unsigned i = 0; i != Order.size(); ++i) {
368 unsigned NewReg = Order[i];
514 // the anti-dependencies in an instruction in order to be effective.
|
| /external/chromium_org/third_party/libjingle/source/talk/base/ |
| bytebuffer.h | 42 ORDER_NETWORK = 0, // Default, use network byte order (big endian).
43 ORDER_HOST, // Use the native order of the host.
46 // |byte_order| defines order of bytes in the buffer.
60 ByteOrder Order() const { return byte_order_; }
|
| /external/chromium_org/third_party/mesa/src/src/egl/main/ |
| eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */
211 /* the order of these entries is the priority */
242 else if (SortInfo[i].Order == SMALLER) {
245 else if (SortInfo[i].Order == LARGER) {
|
| /external/mesa3d/src/egl/main/ |
| eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */
211 /* the order of these entries is the priority */
242 else if (SortInfo[i].Order == SMALLER) {
245 else if (SortInfo[i].Order == LARGER) {
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order;
41 return makeArrayRef(Order.get(), NumRegs);
91 /// getOrder - Returns the preferred allocation order for RC. The order
117 /// Get the minimum register cost in RC's allocation order.
|
| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
85 /// Order - Additional information about Order dependencies.
120 : Dep(S, Order), Contents(), Latency(0) {
132 case Order:
179 /// isNormalMemory - Test if this is an Order dependence between two
183 return getKind() == Order && (Contents.OrdKind == MayAliasMem
187 /// isMustAlias - Test if this is an Order dependence that is marked
191 return getKind() == Order && Contents.OrdKind == MustAliasMem;
199 return getKind() == Order && Contents.OrdKind >= Weak
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| SelectionDAGDumper.cpp | 489 if (unsigned Order = getIROrder())
490 OS << " [ORD=" << Order << ']';
|
| /external/lzma/CPP/7zip/UI/Common/ |
| ZipRegistry.h | 31 UInt32 Order;
42 BlockLogSize = NumThreads = Level = Dictionary = Order = UInt32(-1);
|
| /external/lzma/CS/7zip/ |
| ICoder.cs | 93 /// Specifies order for PPM methods.
95 Order,
|
| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/chromium_org/third_party/leveldatabase/src/doc/bench/ |
| db_bench_tree_db.cc | 12 // Comma-separated list of operations to run in the specified order
15 // fillseq -- write N values in sequential key order in async mode
16 // fillrandom -- write N values in random key order in async mode
17 // overwrite -- overwrite N values in random key order in async mode
18 // fillseqsync -- write N/100 values in sequential key order in sync mode
19 // fillrandsync -- write N/100 values in random key order in sync mode
20 // fillrand100K -- write N/1000 100K values in random order in async mode
21 // fillseq100K -- write N/1000 100K values in seq order in async mode
23 // readseq100K -- read N/1000 100K values in sequential order in async mode
24 // readrand100K -- read N/1000 100K values in sequential order in async mod
[all...] |
| db_bench_sqlite3.cc | 12 // Comma-separated list of operations to run in the specified order
15 // fillseq -- write N values in sequential key order in async mode
16 // fillseqsync -- write N/100 values in sequential key order in sync mode
17 // fillseqbatch -- batch write N values in sequential key order in async mode
18 // fillrandom -- write N values in random key order in async mode
19 // fillrandsync -- write N/100 values in random key order in sync mode
20 // fillrandbatch -- batch write N values in sequential key order in async mode
21 // overwrite -- overwrite N values in random key order in async mode
22 // fillrand100K -- write N/1000 100K values in random order in async mode
23 // fillseq100K -- write N/1000 100K values in sequential order in async mod
[all...] |
| /external/eigen/unsupported/Eigen/src/Splines/ |
| Spline.h | 94 * \brief Evaluation of spline derivatives of up-to given order.
100 * for i ranging between 0 and order.
103 * \param order The order up to which the derivatives are computed.
106 derivatives(Scalar u, DenseIndex order) const;
115 derivatives(Scalar u, DenseIndex order = DerivativeOrder) const;
137 * \brief Computes the non-zero spline basis function derivatives up to given order.
143 * with i ranging from 0 up to the specified order.
147 * \param order The order up to which the basis function derivatives are computes
[all...] |
| /external/chromium_org/third_party/WebKit/Source/devtools/front_end/ |
| DataGrid.js | 142 /** @typedef {{id: ?string, editable: boolean, longText: ?boolean, sort: WebInspector.DataGrid.Order, sortable: boolean, align: WebInspector.DataGrid.Align}} */
153 WebInspector.DataGrid.Order = {
433 return WebInspector.DataGrid.Order.Ascending;
435 return WebInspector.DataGrid.Order.Descending;
575 // width of the parent element is changed in order to make it possible to
726 // header table in order to determine the width of the column, since
[all...] |
| /external/llvm/lib/MC/ |
| MachObjectWriter.cpp | 426 // when we see the attribute, but that makes getting the order in the symbol
496 // The particular order that we collect the symbols and create the string
568 // External and undefined symbols are required to be in lexicographic order.
589 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
590 for (int i = 0, n = Order.size(); i != n ; ++i) {
591 const MCSectionData *SD = Order[i];
865 // Write the section relocation entries, in reverse order to match 'as'
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| StructurizeCFG.cpp | 169 RNVector Order;
276 /// \brief Build up the general order of nodes
280 for (Order.clear(); I != E; ++I) {
282 Order.append(Nodes.begin(), Nodes.end());
430 for (RNVector::reverse_iterator OI = Order.rbegin(), OE = Order.rend();
632 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
633 Order.back()->getEntry();
664 if (Order.empty() && ExitUseAllowed) {
713 /// Take one node from the order vector and wire it u
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order);
854 ArrayRef<Record*> Order = RC.getOrder();
863 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
864 Record *Reg = Order[i];
873 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
874 Record *Reg = Order[i];
[all...] |
| /external/clang/lib/CodeGen/ |
| CGAtomic.cpp | 188 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) {
207 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order);
220 Load->setAtomic(Order);
235 Store->setAtomic(Order);
298 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order);
351 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0;
361 Order = EmitScalarExpr(E->getOrder());
497 Args.add(RValue::get(Order),
499 Order = OrderFail;
502 // int order)
[all...] |
