| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 217 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
218 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
219 if (I == Regs.end())
|
| RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
171 const CodeGenRegister::Set &Regs = RC.getMembers();
172 if (Regs.empty())
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
315 const std::vector<CodeGenRegister*> &Regs,
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 Record *Reg = Regs[i]->TheDef;
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace")
[all...] |
| CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs):
160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
349 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs;
586 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
600 while (!Regs.empty()) {
602 dv = Regs.pop_back_val().Value;
609 DomainValue *Latest = Regs.pop_back_val().Value;
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 592 SmallVector<std::pair<unsigned,bool>, 4> Regs;
624 Regs.push_back(std::make_pair(Reg, isKill));
627 if (Regs.empty())
629 if (Regs.size() > 1 || StrOpc== 0) {
633 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
634 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
635 } else if (Regs.size() == 1) {
638 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
[all...] |
| ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs,
279 /// registers in Regs as the register operands that would be loaded / stored.
287 ArrayRef<std::pair<unsigned, bool> > Regs,
290 unsigned NumRegs = Regs.size();
320 NewBase = Regs[NumRegs-1].first;
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
354 | getKillRegState(Regs[i].second));
393 SmallVector<std::pair<unsigned, bool>, 8> Regs;
400 Regs.push_back(std::make_pair(Reg, isKill));
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 248 SmallVector<SDValue, 4> Regs;
249 Regs.push_back(Val);
253 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
259 Regs.push_back(DAG.getUNDEF(VT));
262 Regs.data(), Regs.size()));
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 826 SmallPtrSet<const SCEV *, 16> &Regs,
839 SmallPtrSet<const SCEV *, 16> &Regs,
843 SmallPtrSet<const SCEV *, 16> &Regs,
853 SmallPtrSet<const SCEV *, 16> &Regs,
875 if (!Regs.count(AR->getOperand(1))) {
876 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
899 /// that refers to one of those regs an instant loser.
901 SmallPtrSet<const SCEV *, 16> &Regs,
909 if (Regs.insert(Reg)) {
910 RateRegister(Reg, Regs, L, SE, DT)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 602 /// Regs - This list holds the registers assigned to the values.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
623 Regs.push_back(Reg + i);
643 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
700 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
