| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 34 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
43 dbgs() << ' ' << PrintReg(Hints[I], TRI);
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| CriticalAntiDepBreaker.h | 38 const TargetRegisterInfo *TRI;
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| RegAllocBase.h | 61 const TargetRegisterInfo *TRI;
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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| DeadMachineInstructionElim.cpp | 32 const TargetRegisterInfo *TRI;
89 TRI = MF.getTarget().getRegisterInfo();
160 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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| ProcessImplicitDefs.cpp | 29 const TargetRegisterInfo *TRI;
110 !TRI->regsOverlap(Reg, UserReg))
145 TRI = MF.getTarget().getRegisterInfo();
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| AggressiveAntiDepBreaker.h | 50 /// (i.e. TRI->getNumRegs()).
121 const TargetRegisterInfo *TRI;
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| BranchFolding.h | 30 const TargetRegisterInfo *tri,
91 const TargetRegisterInfo *TRI;
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| ExpandPostRAPseudos.cpp | 31 const TargetRegisterInfo *TRI;
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
184 TRI = MF.getTarget().getRegisterInfo();
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| RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI;
62 CoalescerPair(const TargetRegisterInfo &tri)
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
69 const TargetRegisterInfo &tri)
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
113 for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 34 const TargetRegisterInfo *TRI;
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| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 82 const TargetRegisterClass *inferRegClass(const TargetRegisterInfo *TRI,
109 const TargetRegisterInfo *TRI,
122 RC = TRI->getCommonSubClass(RC, inferRegClass(TRI, MRI,
133 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
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| /external/llvm/include/llvm/CodeGen/ |
| LiveStackAnalysis.h | 28 const TargetRegisterInfo *TRI;
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| FastISel.h | 59 const TargetRegisterInfo &TRI;
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| LiveRegMatrix.h | 41 const TargetRegisterInfo *TRI;
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| LiveVariables.h | 132 const TargetRegisterInfo *TRI;
200 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
236 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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| ResourcePriorityQueue.h | 60 const TargetRegisterInfo *TRI;
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| RegisterClassInfo.h | 53 const TargetRegisterInfo *TRI;
118 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
127 /// same cost according to TRI->getCostPerUse().
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| RegisterScavenging.h | 32 const TargetRegisterInfo *TRI;
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| VirtRegMap.h | 43 const TargetRegisterInfo *TRI;
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 34 const TargetRegisterInfo *TRI,
40 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
52 const TargetRegisterInfo *TRI,
66 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
147 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
160 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
192 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
197 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
215 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
219 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 58 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPrologEpilogPass.cpp | 50 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
61 TRI.eliminateFrameIndex(MI, 0, i, NULL);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex)
[all...] |
