| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 335 bool isKill = Op.hasOneUse() &&
339 if (isKill) {
347 isKill = false;
350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 268 bool isKill = BaseReg != ARM::SP;
272 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
|
| Thumb1FrameLowering.cpp | 348 bool isKill = true;
357 isKill = false;
360 if (isKill)
363 MIB.addReg(Reg, getKillRegState(isKill));
|
| ARMFrameLowering.cpp | 608 bool isKill = true;
612 isKill = false;
615 if (isKill)
624 Regs.push_back(std::make_pair(Reg, isKill));
[all...] |
| ARMLoadStoreOptimizer.cpp | 82 bool isKill;
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
386 if (memOps[i].Position < insertPos && memOps[i].isKill) {
399 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
400 Regs.push_back(std::make_pair(Reg, isKill));
430 memOps[j].isKill = false;
432 memOps[i].isKill = true;
716 bool BaseKill = MI->getOperand(0).isKill();
852 bool BaseKill = MI->getOperand(1).isKill();
[all...] |
| ARMBaseInstrInfo.cpp | 248 if (MO.isUse() && MO.isKill()) {
758 unsigned SrcReg, bool isKill, int FI,
777 .addReg(SrcReg, getKillRegState(isKill))
781 .addReg(SrcReg, getKillRegState(isKill))
789 .addReg(SrcReg, getKillRegState(isKill))
794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
805 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
817 .addReg(SrcReg, getKillRegState(isKill))
821 .addReg(SrcReg, getKillRegState(isKill))
834 .addReg(SrcReg, getKillRegState(isKill))
[all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 154 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
178 .addReg(Reg, getKillRegState(isKill))
199 .addReg(Reg, getKillRegState(isKill))
228 .addReg(Reg, getKillRegState(isKill))
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 139 if (MO.isKill())
148 if (MO.isKill())
198 bool isKill = KilledUseSet.count(Reg);
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
307 PRI.Kills = MO.isKill();
|
| LiveIntervalAnalysis.cpp | 819 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
834 if (!isKill)
[all...] |
| MachineLICM.cpp | 773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
827 bool isKill = isOperandKill(MO, MRI);
828 if (isNew && !isKill)
831 else if (!isNew && isKill)
[all...] |
| TwoAddressInstructionPass.cpp | 233 if (!UseMO.isKill())
276 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
811 if (MOReg != Reg && (MO.isKill() ||
862 bool isKill = MO.isKill() ||
865 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
868 if (MOReg == Reg && !isKill)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 79 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
90 /// IsKill - True if this instruction is the last use of the register on this
92 bool IsKill : 1;
289 bool isKill() const {
291 return IsKill;
370 IsKill = Val;
516 /// operand. Note: This method ignores isKill and isDead properties.
535 bool isKill = false, bool isDead = false,
561 bool isKill = false, bool isDead = false,
570 Op.IsKill = isKill
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
