| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 78 /* NOTE: must be kept in sync with enum ArmOpcode from LIR.h */
1006 LIR* lir; local
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 77 /* NOTE: must be kept in sync with enum MipsOpcode from LIR.h */
460 void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) {
463 int opcode = lir->opcode;
464 int dalvik_offset = lir->dalvik_offset;
482 LIR* hop_target = NULL;
485 LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0],
486 lir->operands[1], 0, 0, 0, hop_target);
487 InsertLIRBefore(lir, hop_branch)
516 LIR *lir; local
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 1164 LIR *lir; local
[all...] |
| /art/compiler/dex/quick/ |
| codegen_util.cc | 47 void Mir2Lir::MarkSafepointPC(LIR* inst) {
49 LIR* safepoint_pc = NewLIR0(kPseudoSafepointPC);
59 void Mir2Lir::NopLIR(LIR* lir) {
60 lir->flags.is_nop = true;
63 void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type) {
66 DCHECK(GetTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE));
68 mask_ptr = &lir->use_mask;
70 mask_ptr = &lir->def_mask
696 LIR* lir; local
[all...] |
| /external/qemu/android/skin/ |
| trackball.c | 344 double lir = 1/sqrt(lx*lx + ly*ly + lz*lz); local
345 double cosphi = lir*(lx*rx + ly*ry + lz*rz);
|
| /dalvik/vm/compiler/codegen/arm/ |
| Assemble.cpp | 941 ArmLIR *lir; local
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | 431 * Assemble the LIR into binary instruction format. Note that we may
440 MipsLIR *lir; local
442 for (lir = (MipsLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
443 if (lir->opcode < 0) {
448 if (lir->flags.isNop) {
452 if (lir->opcode == kMipsB || lir->opcode == kMipsBal)
[all...] |
