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Searched
refs:ADDiu
(Results
1 - 8
of
8
) sorted by null
/external/llvm/lib/Target/Mips/
MipsAnalyzeImmediate.cpp
32
AddInstr(SeqLs, Inst(
ADDiu
, Imm & 0xffffULL));
56
// A single
ADDiu
will do if RemSize <= 16.
58
AddInstr(SeqLs, Inst(
ADDiu
, MaskedImm));
71
// instruction is an
ADDiu
or ORi. In that case, do not call GetInstSeqLsORi.
79
// Replace a
ADDiu
& SLL pair with a LUi.
81
//
ADDiu
0x0111
86
// Check if the first two instructions are
ADDiu
and SLL and the shift amount
88
if ((Seq.size() < 2) || (Seq[0].Opc !=
ADDiu
) ||
92
// Sign-extend and shift operand of
ADDiu
and see if it still fits in 16-bit.
130
ADDiu
= Mips::ADDiu
[
all
...]
MipsAnalyzeImmediate.h
26
/// instruction in the sequence must be an
ADDiu
if LastInstrIsADDiu is
35
/// GetInstSeqLsADDiu - Get instrucion sequences which end with an
ADDiu
to
50
/// ReplaceADDiuSLLWithLUi - Replace an
ADDiu
& SLL pair with a LUi.
58
unsigned
ADDiu
, ORi, SLL, LUi;
MipsLongBranch.cpp
273
//
addiu
$sp, $sp, -8
278
//
addiu
$at, $at, %lo($tgt - $baltgt)
282
//
addiu
$sp, $sp, 8
288
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::
ADDiu
), Mips::SP)
299
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::
ADDiu
), Mips::AT)
308
.append(BuildMI(*MF, DL, TII->get(Mips::
ADDiu
), Mips::SP)
401
BuildMI(MBB, I, DL, TII->get(Mips::
ADDiu
), Mips::V0)
MipsSEISelDAGToDAG.cpp
73
// Check if MI is "
addiu
$dst, $zero, 0" or "daddiu $dst, $zero, 0".
74
if ((MI.getOpcode() == Mips::
ADDiu
) &&
150
//
addiu
$globalbasereg, $v0, %lo(__gnu_local_gp)
153
BuildMI(MBB, I, DL, TII.get(Mips::
ADDiu
), GlobalBaseReg).addReg(V0)
164
//
addiu
$globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
169
BuildMI(MBB, I, DL, TII.get(Mips::
ADDiu
), GlobalBaseReg).addReg(V1)
180
// 1.
addiu
$2, $2, %lo(_gp_disp)
191
// the value instruction 1 (
addiu
) defines is valid when instruction 2 (addu)
284
//
addiu
$2, $2, %lo($CPI1_0)
383
// instructions (
ADDiu
, ORI and SLL) in that it does not have a registe
[
all
...]
MipsSEInstrInfo.cpp
320
unsigned
ADDiu
= STI.isABI_N64() ? Mips::DADDiu : Mips::
ADDiu
;
323
BuildMI(MBB, I, DL, get(
ADDiu
), SP).addReg(SP).addImm(Amount);
353
// instructions (
ADDiu
, ORI and SLL) in that it does not have a register
MipsSEISelLowering.cpp
800
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::
ADDiu
), VR2)
806
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::
ADDiu
), VR1)
MipsISelLowering.cpp
[
all
...]
/external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp
546
// li d,j =>
addiu
d,$zero,j
547
tmpInst.setOpcode(Mips::
ADDiu
);
582
// la d,j(s) =>
addiu
d,s,j
583
tmpInst.setOpcode(Mips::
ADDiu
);
622
// la d,j =>
addiu
d,$zero,j
623
tmpInst.setOpcode(Mips::
ADDiu
);
[
all
...]
Completed in 551 milliseconds