/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 343 SmallVector<CCValAssign, 16> ArgLocs; 345 getTargetMachine(), ArgLocs, *DAG.getContext()); 350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 351 CCValAssign &VA = ArgLocs[i]; 372 CCValAssign &NextVA = ArgLocs[++i]; 541 SmallVector<CCValAssign, 16> ArgLocs; 543 getTargetMachine(), ArgLocs, *DAG.getContext()); 549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 550 CCValAssign &VA = ArgLocs[i]; 670 SmallVector<CCValAssign, 16> ArgLocs; [all...] |
/art/compiler/dex/quick/x86/ |
call_x86.cc | 215 void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 250 FlushIns(ArgLocs, rl_method);
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codegen_x86.h | 120 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
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/art/compiler/dex/quick/mips/ |
call_mips.cc | 321 void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 359 FlushIns(ArgLocs, rl_method);
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codegen_mips.h | 120 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 325 SmallVector<CCValAssign, 16> ArgLocs; 327 getTargetMachine(), ArgLocs, *DAG.getContext()); 336 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 337 CCValAssign &VA = ArgLocs[i]; 471 SmallVector<CCValAssign, 16> ArgLocs; 473 getTargetMachine(), ArgLocs, *DAG.getContext()); 489 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 490 CCValAssign &VA = ArgLocs[i]; [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 398 SmallVector<CCValAssign, 16> ArgLocs; 400 getTargetMachine(), ArgLocs, *DAG.getContext()); 433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ 434 CCValAssign &VA = ArgLocs[i]; 457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 458 CCValAssign &VA = ArgLocs[i]; 828 SmallVector<CCValAssign, 16> ArgLocs; 830 getTargetMachine(), ArgLocs, *DAG.getContext()); 843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 844 CCValAssign &VA = ArgLocs[i] [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |
/art/compiler/dex/quick/arm/ |
call_arm.cc | 554 void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 598 FlushIns(ArgLocs, rl_method);
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codegen_arm.h | 119 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
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/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | 185 SmallVector<CCValAssign, 16> ArgLocs; 187 getTargetMachine(), ArgLocs, *DAG.getContext()); 213 CCValAssign &VA = ArgLocs[ArgIdx++]; 251 Reg = ArgLocs[ArgIdx++].getLocReg(); [all...] |
R600ISelLowering.cpp | [all...] |
/art/compiler/dex/quick/ |
mir_to_lir.h | 467 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 621 virtual void GenEntrySequence(RegLocation* ArgLocs, [all...] |
gen_invoke.cc | 233 * ArgLocs is an array of location records describing the incoming arguments 236 void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 275 RegLocation* t_loc = &ArgLocs[i]; [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 588 SmallVector<CCValAssign, 16> ArgLocs; 589 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext()); 594 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 596 CCValAssign &VA = ArgLocs[I]; 712 SmallVector<CCValAssign, 16> ArgLocs; 713 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext()); 727 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 728 CCValAssign &VA = ArgLocs[I]; [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
X86FastISel.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |