| /external/valgrind/main/VEX/test/ |
| test-i386-shift.h | 37 flags &= ~CC_O;
50 flags &= ~CC_O;
73 flags &= ~CC_O;
86 flags &= ~CC_O;
102 flags &= ~CC_O;
118 flags_in = (o ? CC_O : 0)
|
| test-amd64-shift.h | 38 flags &= ~CC_O;
51 flags &= ~CC_O;
64 flags &= ~CC_O;
87 flags &= ~CC_O;
100 flags &= ~CC_O;
116 flags &= ~CC_O;
132 flags_in = (o ? CC_O : 0)
|
| test-amd64.c | 61 #define CC_O 0x0800
67 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
116 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
357 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
359 #define CC_MASK (CC_O | CC_C)
860 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
861 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1183 rflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
[all...] |
| test-i386.c | 51 #define CC_O 0x0800
57 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
106 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
345 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
347 #define CC_MASK (CC_O | CC_C)
822 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
823 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1143 eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
[all...] |
| test-i386.h | 125 flags_in = (o ? CC_O : 0)
|
| test-amd64.h | 116 flags_in = (o ? CC_O : 0)
|
| /external/qemu/target-i386/ |
| helper_template.h | 66 of = lshift((src1 ^ src2 ^ -1) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O;
90 of = lshift((src1 ^ src2 ^ -1) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O;
114 of = lshift((src1 ^ src2) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O;
139 of = lshift((src1 ^ src2) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O;
216 of = lshift(CC_SRC ^ CC_DST, 12 - DATA_BITS) & CC_O;
241 of = lshift(CC_SRC ^ CC_DST, 12 - DATA_BITS) & CC_O;
290 env->cc_tmp = (eflags & ~(CC_C | CC_O)) |
291 (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |
319 env->cc_tmp = (eflags & ~(CC_C | CC_O)) |
320 (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |
[all...] |
| exec.h | 279 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
| cpu.h | 106 #define CC_O 0x0800
|
| helper.c | 698 eflags & CC_O ? 'O' : '-',
725 eflags & CC_O ? 'O' : '-',
[all...] |
| op_helper.c | [all...] |
| translate.c | 871 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
879 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
[all...] |
| /external/valgrind/main/none/tests/amd64/ |
| amd64locked.c | 215 #define CC_O 0x0800
217 #define CC_MASK (CC_C | CC_P | CC_A | CC_Z | CC_S | CC_O)
237 flags_in = (o ? CC_O : 0) \
331 flags_in = (o ? CC_O : 0) \
447 flags_in = (o ? CC_O : 0) \
|
| /external/valgrind/main/none/tests/x86/ |
| x86locked.c | 200 #define CC_O 0x0800
202 #define CC_MASK (CC_C | CC_P | CC_A | CC_Z | CC_S | CC_O)
222 flags_in = (o ? CC_O : 0) \
309 flags_in = (o ? CC_O : 0) \
411 flags_in = (o ? CC_O : 0) \
|
| /external/valgrind/main/memcheck/tests/amd64/ |
| more_x87_fp.c | 67 #define CC_O 0x0800
|
| /external/valgrind/main/memcheck/tests/x86/ |
| more_x86_fp.c | 57 #define CC_O 0x0800
|
| /external/qemu/ |
| cpu-exec.c | 277 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
280 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
615 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.h | 196 CC_O = 0x17
|
| nv50_ir_lowering_nv50.cpp | 639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
|
| nv50_ir_emit_nv50.cpp | 219 case CC_O: enc = 0x10; break;
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.h | 196 CC_O = 0x17
|
| nv50_ir_lowering_nv50.cpp | 639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
|
| nv50_ir_emit_nv50.cpp | 219 case CC_O: enc = 0x10; break;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_emit_nvc0.cpp | 216 case CC_O: val = 0x17; break;
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_emit_nvc0.cpp | 216 case CC_O: val = 0x17; break;
[all...] |
