/external/clang/test/SemaTemplate/ |
value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { 6 return Cond? "honk" : N; 9 const char *f1(bool Cond) { 10 return Cond? N : "honk";
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/ndk/tests/device/issue42891-boost-1_52/jni/boost/boost/utility/ |
enable_if.hpp | 35 template <class Cond, class T = void> 36 struct enable_if : public enable_if_c<Cond::value, T> {}; 46 template <class Cond, class T> 47 struct lazy_enable_if : public lazy_enable_if_c<Cond::value, T> {}; 58 template <class Cond, class T = void> 59 struct disable_if : public disable_if_c<Cond::value, T> {}; 69 template <class Cond, class T> 70 struct lazy_disable_if : public lazy_disable_if_c<Cond::value, T> {}; 99 template <class Cond, class T = detail::enable_if_default_T> 103 template <class Cond, class T = detail::enable_if_default_T> [all...] |
/external/llvm/lib/Target/Mips/ |
MipsInstrInfo.cpp | 70 SmallVectorImpl<MachineOperand> &Cond) const { 77 Cond.push_back(MachineOperand::CreateImm(Opc)); 80 Cond.push_back(Inst->getOperand(i)); 86 SmallVectorImpl<MachineOperand> &Cond, 89 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 96 const SmallVectorImpl<MachineOperand>& Cond) 98 unsigned Opc = Cond[0].getImm(); 102 for (unsigned i = 1; i < Cond.size(); ++i) { 103 if (Cond[i].isReg()) 104 MIB.addReg(Cond[i].getReg()) [all...] |
MipsInstrInfo.h | 51 SmallVectorImpl<MachineOperand> &Cond, 58 const SmallVectorImpl<MachineOperand> &Cond, 62 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 66 SmallVectorImpl<MachineOperand> &Cond, 131 SmallVectorImpl<MachineOperand> &Cond) const; 134 const SmallVectorImpl<MachineOperand>& Cond) const;
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/ndk/tests/device/issue42891-boost-1_52/jni/boost/boost/iterator/detail/ |
enable_if.hpp | 66 template <class Cond, 70 : enabled<(Cond::value)>::template base<Return>
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
ConstraintManager.h | 68 DefinedSVal Cond, 75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { 76 ProgramStateRef StTrue = assume(State, Cond, true); 78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary 86 assert(assume(State, Cond, false) && "System is over constrained."); 91 ProgramStateRef StFalse = assume(State, Cond, false);
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/external/clang/lib/StaticAnalyzer/Core/ |
SimpleConstraintManager.h | 36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond, 39 ProgramStateRef assume(ProgramStateRef state, Loc Cond, bool Assumption); 41 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption); 90 Loc Cond, 94 NonLoc Cond,
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SimpleConstraintManager.cpp | 69 DefinedSVal Cond, 71 if (Optional<NonLoc> NV = Cond.getAs<NonLoc>()) 73 return assume(state, Cond.castAs<Loc>(), Assumption); 76 ProgramStateRef SimpleConstraintManager::assume(ProgramStateRef state, Loc cond, 78 state = assumeAux(state, cond, assumption); 80 return SU->processAssume(state, cond, assumption); 85 Loc Cond, bool Assumption) { 86 switch (Cond.getSubKind()) { 93 const MemRegion *R = Cond.castAs<loc::MemRegionVal>().getRegion(); 111 bool b = Cond.castAs<loc::ConcreteInt>().getValue() != 0 [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreInstrInfo.cpp | 189 SmallVectorImpl<MachineOperand> &Cond, 222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 223 Cond.push_back(LastInst->getOperand(0)); 244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 245 Cond.push_back(SecondLastInst->getOperand(0)); 277 const SmallVectorImpl<MachineOperand> &Cond, 281 assert((Cond.size() == 2 || Cond.size() == 0) && 285 if (Cond.empty()) { 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()) [all...] |
XCoreInstrInfo.h | 54 SmallVectorImpl<MachineOperand> &Cond, 59 const SmallVectorImpl<MachineOperand> &Cond, 82 SmallVectorImpl<MachineOperand> &Cond) const;
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/external/clang/test/SemaCXX/ |
vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, 43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; 44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; 45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; 46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; 49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; 50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; 51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; 52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; 55 (void)(Cond? c16 : ll16) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 69 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
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NVPTXInstrInfo.cpp | 169 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { 186 Cond.push_back(LastInst->getOperand(0)); 204 Cond.push_back(SecondLastInst->getOperand(0)); 250 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { 253 assert((Cond.size() == 1 || Cond.size() == 0) && 258 if (Cond.empty()) // Unconditional branch 261 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 267 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_emulate_loops.h | 12 struct rc_instruction * Cond;
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radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, 200 loop->Cond->U.I.SrcReg[0].Index)){ 201 limit = &loop->Cond->U.I.SrcReg[0]; 202 counter = &loop->Cond->U.I.SrcReg[1]; 204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, 205 loop->Cond->U.I.SrcReg[1].Index)){ 206 limit = &loop->Cond->U.I.SrcReg[1]; 207 counter = &loop->Cond->U.I.SrcReg[0]; 285 switch(loop->Cond->U.I.Opcode){ 309 rc_remove_instruction(loop->Cond); [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_emulate_loops.h | 12 struct rc_instruction * Cond;
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radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, 200 loop->Cond->U.I.SrcReg[0].Index)){ 201 limit = &loop->Cond->U.I.SrcReg[0]; 202 counter = &loop->Cond->U.I.SrcReg[1]; 204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, 205 loop->Cond->U.I.SrcReg[1].Index)){ 206 limit = &loop->Cond->U.I.SrcReg[1]; 207 counter = &loop->Cond->U.I.SrcReg[0]; 285 switch(loop->Cond->U.I.Opcode){ 309 rc_remove_instruction(loop->Cond); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430InstrInfo.h | 74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 78 SmallVectorImpl<MachineOperand> &Cond, 84 const SmallVectorImpl<MachineOperand> &Cond,
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MSP430InstrInfo.cpp | 127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 128 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 154 Cond[0].setImm(CC); 172 SmallVectorImpl<MachineOperand> &Cond, 207 Cond.clear(); 231 if (Cond.empty()) { 234 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 240 assert(Cond.size() == 1); 248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm() [all...] |
MSP430BranchSelector.cpp | 150 SmallVector<MachineOperand, 1> Cond; 151 Cond.push_back(I->getOperand(1)); 154 TII->ReverseBranchCondition(Cond); 156 .addImm(4).addOperand(Cond[0]);
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/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 59 SmallVectorImpl<MachineOperand> &Cond, 63 const SmallVectorImpl<MachineOperand> &Cond, 66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/external/chromium_org/sandbox/linux/seccomp-bpf/ |
sandbox_bpf_unittest.cc | 286 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, 0, 301 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, 0, 771 // Simple test demonstrating how to use Sandbox::Cond() 786 return sandbox->Cond(1, ErrorCode::TP_32BIT, ErrorCode::OP_HAS_ANY_BITS, 793 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, 796 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, 819 // This test exercises the Sandbox::Cond() method by building a complex [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcInstrInfo.h | 67 SmallVectorImpl<MachineOperand> &Cond, 74 const SmallVectorImpl<MachineOperand> &Cond,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, 216 Cond.push_back(predSet->getOperand(1)); 217 Cond.push_back(predSet->getOperand(2)); 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 240 Cond.push_back(predSet->getOperand(1)); 241 Cond.push_back(predSet->getOperand(2)); 242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 264 const SmallVectorImpl<MachineOperand> &Cond, 270 if (Cond.empty()) { 277 PredSet->getOperand(2).setImm(Cond[1].getImm()) [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, 216 Cond.push_back(predSet->getOperand(1)); 217 Cond.push_back(predSet->getOperand(2)); 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 240 Cond.push_back(predSet->getOperand(1)); 241 Cond.push_back(predSet->getOperand(2)); 242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 264 const SmallVectorImpl<MachineOperand> &Cond, 270 if (Cond.empty()) { 277 PredSet->getOperand(2).setImm(Cond[1].getImm()) [all...] |