| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 193 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 816 MVT DestVT = TLI->getRegisterType(NewVT);
817 RegisterVT = DestVT;
818 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
819 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeDAG.cpp | 120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
[all...] |
| LegalizeTypes.cpp | [all...] |
| LegalizeTypes.h | 154 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
[all...] |
| LegalizeVectorTypes.cpp | 228 EVT DestVT = N->getValueType(0).getVectorElementType();
230 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
