| /external/valgrind/main/cachegrind/ |
| cg-ppc32.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
44 *I1c = (cache_t) { 65536, 2, 64 };
|
| cg-ppc64.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
44 *I1c = (cache_t) { 65536, 2, 64 };
|
| cg-s390x.c | 42 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
106 *I1c = (cache_t) { 65536, 4, 256 };
|
| cg-arm.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
44 *I1c = (cache_t) { 16384, 4, 64 };
|
| cg-mips32.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
44 *I1c = (cache_t) { 32768, 4, 32 };
|
| cg_arch.h | 49 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
66 void VG_(post_clo_init_configure_caches)(cache_t* I1c,
|
| cg-x86-amd64.c | 62 Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* LLc)
121 case 0x06: *I1c = (cache_t) { 8, 4, 32 }; break;
122 case 0x08: *I1c = (cache_t) { 16, 4, 32 }; break;
123 case 0x09: *I1c = (cache_t) { 32, 4, 64 }; break;
124 case 0x30: *I1c = (cache_t) { 32, 8, 64 }; break;
207 *I1c = (cache_t) { 16, 8, 32 };
211 *I1c = (cache_t) { 16, 8, 32 };
215 *I1c = (cache_t) { 32, 8, 32 };
265 case 2: *I1c = c; break;
366 Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* LLc
[all...] |
| cg-arch.c | 160 void VG_(post_clo_init_configure_caches)(cache_t* I1c,
177 VG_(configure_caches)( I1c, D1c, LLc, all_caches_clo_defined );
182 check_cache_or_override ("I1", I1c, DEFINED(clo_I1c));
188 if (DEFINED(clo_I1c)) { *I1c = *clo_I1c; }
194 umsg_cache_img ("I1", I1c);
|
| cg_main.c | [all...] |
| /external/valgrind/main/callgrind/ |
| sim.c | [all...] |
