/external/llvm/include/llvm/Target/ |
TargetOpcodes.h | 43 /// INSERT_SUBREG - This instruction takes three operands: a register that 49 INSERT_SUBREG = 7, 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/external/llvm/lib/CodeGen/ |
ExpandPostRAPseudos.cpp | 90 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 217 case TargetOpcode::INSERT_SUBREG:
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/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 651 return getOpcode() == TargetOpcode::INSERT_SUBREG; 691 case TargetOpcode::INSERT_SUBREG: [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 265 case TargetOpcode::INSERT_SUBREG: 305 case TargetOpcode::INSERT_SUBREG:
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InstrEmitter.cpp | 511 } else if (Opc == TargetOpcode::INSERT_SUBREG || 521 // the INSERT_SUBREG instruction. 523 // %dst = INSERT_SUBREG %src, %sub, SubIdx 534 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 539 // Create the insert_subreg or subreg_to_reg machine instruction. 557 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 701 Opc == TargetOpcode::INSERT_SUBREG || [all...] |
ScheduleDAGRRList.cpp | [all...] |
SelectionDAG.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 54 case TargetOpcode::INSERT_SUBREG: 106 case TargetOpcode::INSERT_SUBREG:
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/external/llvm/lib/Target/R600/ |
R600OptimizeVectorRegisters.cpp | 23 /// vreg7<def> = INSERT_SUBREG vreg4, sub3 191 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
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/external/llvm/lib/Target/ARM/ |
A15SDOptimizer.cpp | 267 // See if the first operand of this insert_subreg is IMPLICIT_DEF 338 // INSERT_SUBREG or REG_SEQUENCE. 510 TII->get(TargetOpcode::INSERT_SUBREG), Out) 586 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and 602 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
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ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 787 SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, [all...] |
SystemZISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |