| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 544 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
549 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
554 IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES | SETS_CCODES,
577 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
581 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
585 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
589 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
593 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
597 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
[all...] |
| utility_arm.cc | 340 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) {
410 if (EncodingMap[opcode].flags & IS_QUAD_OP) {
536 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP)
|
| /dalvik/vm/compiler/codegen/arm/ |
| Assemble.cpp | 544 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
549 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
554 IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES | SETS_CCODES,
577 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
581 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
585 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
589 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
593 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
597 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
[all...] |
| ArmLIR.h | 696 #define IS_QUAD_OP (1 << kIsQuadOp)
[all...] |
| CodegenCommon.cpp | 324 (EncodingMap[opcode].flags & IS_QUAD_OP));
|
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 147 kFmtBitBlt, 20, 16, IS_QUAD_OP | REG_DEF01 | REG_USE23,
152 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
399 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
403 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
407 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0_USE0 | NEEDS_FIXUP,
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir-inl.h | 106 DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP))
|
| mir_to_lir.h | 40 #define IS_QUAD_OP (1ULL << kIsQuadOp)
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 132 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },
136 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },
139 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },
240 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
241 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
243 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
244 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
245 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
246 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| CodegenCommon.cpp | 331 (EncodingMap[opcode].flags & IS_QUAD_OP));
|
| MipsLIR.h | 540 #define IS_QUAD_OP (1 << kIsQuadOp)
|
| Assemble.cpp | 143 kFmtBitBlt, 20, 16, IS_QUAD_OP | REG_DEF01 | REG_USE23,
148 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Factory.cpp | 414 } else if (EncodingMap[opcode].flags & IS_QUAD_OP)
484 if (EncodingMap[opcode].flags & IS_QUAD_OP)
611 if (EncodingMap[altOpcode].flags & IS_QUAD_OP)
[all...] |
