/external/llvm/lib/Target/X86/Utils/ |
X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 44 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm, 67 void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { 31 unsigned ZMask = Imm & 15; 32 unsigned CountD = (Imm >> 4) & 3; 33 unsigned CountS = (Imm >> 6) & 3; 64 void DecodePALIGNRMask(MVT VT, unsigned Imm, 67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); 85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { 91 unsigned NewImm = Imm; 97 if (NumLaneElts == 4) NewImm = Imm; // reload imm [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm 109 // reg, the second is the shift amount (or reg0 if not present or imm). The 110 // third operand encodes the shift opcode and the imm if a reg isn't present. 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 123 /// the 8-bit imm value. 124 static inline unsigned getSOImmValImm(unsigned Imm) { 125 return Imm & 0xFF [all...] |
/external/llvm/lib/Target/Mips/ |
MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, 31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, 37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, 43 unsigned Shamt = countTrailingZeros(Imm); 44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize [all...] |
MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instrucion sequence to load immediate Imm. The last 28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 36 /// load immediate Imm 37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 40 /// load immediate Imm 41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 44 /// load immediate Imm 45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 47 /// GetInstSeqLs - Get instrucion sequences to load immediate Imm. 48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs) [all...] |
Mips16InstrInfo.h | 87 int64_t Imm, MachineBasicBlock &MBB, 92 int64_t Imm, MachineBasicBlock &MBB, 103 // build the proper one based on the Imm field 106 const MCInstrDesc& AddiuSpImm(int64_t Imm) const; 109 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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MipsISelDAGToDAG.h | 56 /// (reg + imm). 76 inline SDValue getImm(const SDNode *Node, uint64_t Imm) { 77 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
SIMCCodeEmitter.cpp | 86 IntFloatUnion Imm; 88 Imm.I = MO.getImm(); 90 Imm.F = MO.getFPImm(); 94 if (Imm.I >= 0 && Imm.I <= 64) 95 return 128 + Imm.I; 97 if (Imm.I >= -16 && Imm.I <= -1) 98 return 192 + abs(Imm.I); 100 if (Imm.F == 0.5f [all...] |
/external/llvm/lib/MC/ |
MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm(); 20 Target = Addr+Size+Imm;
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/external/llvm/lib/Target/SystemZ/Disassembler/ |
SystemZDisassembler.cpp | 106 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { 107 assert(isUInt<N>(Imm) && "Invalid immediate"); 108 Inst.addOperand(MCOperand::CreateImm(Imm)); 113 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { 114 assert(isUInt<N>(Imm) && "Invalid immediate"); 115 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); 119 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, 122 return decodeUImmOperand<4>(Inst, Imm); 125 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, 127 return decodeUImmOperand<4>(Inst, Imm); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFastISel.cpp | 97 unsigned PPCMaterialize32BitInt(int64_t Imm, 99 unsigned PPCMaterialize64BitInt(int64_t Imm, 156 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm, 158 unsigned Lo = Imm & 0xFFFF; 159 unsigned Hi = (Imm >> 16) & 0xFFFF; 164 if (isInt<16>(Imm)) 167 .addImm(Imm); 188 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm, 195 if (!isInt<32>(Imm)) { 196 Shift = countTrailingZeros<uint64_t>(Imm); [all...] |
PPCISelDAGToDAG.cpp | 74 inline SDValue getI32Imm(unsigned Imm) { 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 80 inline SDValue getI64Imm(uint64_t Imm) { 81 return CurDAG->getTargetConstant(Imm, MVT::i64); 85 inline SDValue getSmallIPtrImm(unsigned Imm) { 86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 116 /// a base register plus a signed 16-bit displacement [r+imm]. 137 /// be represented by [r+imm], which are preferred. 281 static bool isIntS16Immediate(SDNode *N, short &Imm) { 285 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue() [all...] |
/external/llvm/lib/Target/NVPTX/InstPrinter/ |
NVPTXInstPrinter.cpp | 87 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">"); 97 int64_t Imm = MO.getImm(); 101 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) 105 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) 109 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { 147 int64_t Imm = MO.getImm(); 151 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) 154 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { 221 int Imm = (int) MO.getImm(); 223 if (Imm) [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 56 int32_t Imm = unpackSignedImm(9, MOImm.getImm()); 58 O << '#' << Imm; 98 assert(Imm12 >= 0 && "Invalid immediate for add/sub imm"); 247 uint32_t Imm = MOImm.getImm() * MemSize; 249 O << "#" << Imm; 366 int32_t Imm = unpackSignedImm(7, MOImm.getImm()); 368 O << "#" << (Imm * MemScale); 425 int64_t Imm = MO.getImm(); 428 if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1 [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIInstrInfo.h | 46 int64_t Imm) const;
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SIInstrInfo.cpp | 53 int64_t Imm) const 57 MachineInstrBuilder(MI).addImm(Imm);
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIInstrInfo.h | 46 int64_t Imm) const;
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SIInstrInfo.cpp | 53 int64_t Imm) const 57 MachineInstrBuilder(MI).addImm(Imm);
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/external/llvm/lib/IR/ |
AutoUpgrade.cpp | 237 unsigned Imm; 239 Imm = 0; 241 Imm = 1; 243 Imm = 2; 245 Imm = 3; 247 Imm = 4; 249 Imm = 5; 251 Imm = 6; 253 Imm = 7; 259 CI->getArgOperand(1), Builder.getInt8(Imm)); [all...] |
/external/llvm/include/llvm/CodeGen/ |
FastISel.h | 208 uint64_t Imm); 227 uint64_t Imm); 237 uint64_t Imm, MVT ImmType); 244 uint64_t Imm); 285 uint64_t Imm); 306 uint64_t Imm); 320 uint64_t Imm);
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/external/llvm/include/llvm/Analysis/ |
TargetTransformInfo.h | 217 virtual bool isLegalAddImmediate(int64_t Imm) const; 223 virtual bool isLegalICmpImmediate(int64_t Imm) const; 267 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86IntelInstPrinter.cpp | 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 55 switch (Imm) { 78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 79 switch (Imm) {
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/external/llvm/lib/Target/NVPTX/ |
NVPTXISelDAGToDAG.h | 71 inline SDValue getI32Imm(unsigned Imm) { 72 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/llvm/lib/Analysis/ |
TargetTransformInfo.cpp | 99 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const { 100 return PrevTTI->isLegalAddImmediate(Imm); 103 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const { 104 return PrevTTI->isLegalICmpImmediate(Imm); 148 unsigned TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const { 149 return PrevTTI->getIntImmCost(Imm, Ty); 460 bool isLegalAddImmediate(int64_t Imm) const { 464 bool isLegalICmpImmediate(int64_t Imm) const { 508 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const {
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/external/llvm/utils/TableGen/ |
PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg }; 31 uint64_t Imm; // Integer immedate value. 104 OperandMap[BaseIdx + i].Kind = OpData::Imm; 105 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 235 case OpData::Imm: 237 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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