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    Searched refs:IsWrite (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Transforms/Instrumentation/
AddressSanitizer.cpp 285 Value *Addr, uint32_t TypeSize, bool IsWrite,
290 bool IsWrite, size_t AccessSizeIndex,
295 Instruction *InsertBefore, bool IsWrite);
579 Value *Addr, Value *Size, Instruction *InsertBefore, bool IsWrite) {
584 instrumentAddress(OrigIns, InsertBefore, Addr, 8, IsWrite, Size);
590 instrumentAddress(OrigIns, InsertBefore, AddrLast, 8, IsWrite, Size);
620 // and set IsWrite. Otherwise return NULL.
621 static Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite) {
624 *IsWrite = false;
629 *IsWrite = true
    [all...]
ThreadSanitizer.cpp 399 bool IsWrite = isa<StoreInst>(*I);
400 Value *Addr = IsWrite
406 if (IsWrite && isVtableAccess(I)) {
419 if (!IsWrite && isVtableAccess(I)) {
425 Value *OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx];
427 if (IsWrite) NumInstrumentedWrites++;
  /external/compiler-rt/lib/tsan/tests/unit/
tsan_shadow_test.cc 28 EXPECT_EQ(s.IsWrite(), true);
  /external/compiler-rt/lib/tsan/rtl/
tsan_rtl.h 256 DCHECK_EQ(kAccessIsWrite, IsWrite());
319 bool IsWrite() const { return !IsRead(); }
349 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic));
357 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite));
365 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite));
tsan_rtl_report.cc 164 mop->write = s.IsWrite();
  /external/llvm/lib/Transforms/Vectorize/
LoopVectorize.cpp     [all...]

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