| /external/apache-xml/src/main/java/org/apache/xpath/compiler/ |
| OpCodes.java | 94 * [OP_AND]
103 public static final int OP_AND = 3;
|
| Compiler.java | 127 case OpCodes.OP_AND :
[all...] |
| XPathParser.java | 839 insertOp(opPos, 2, OpCodes.OP_AND);
[all...] |
| /external/chromium_org/third_party/angle_dx11/src/compiler/preprocessor/ |
| Token.h | 37 OP_AND,
|
| ExpressionParser.y | 212 case pp::Token::OP_AND: type = TOK_OP_AND; break;
|
| Tokenizer.l | 168 return pp::Token::OP_AND;
|
| ExpressionParser.cpp | [all...] |
| /external/chromium_org/third_party/angle_dx11/tests/preprocessor_tests/ |
| operator_test.cpp | 63 {"&&", pp::Token::OP_AND},
|
| /system/core/libpixelflinger/codeflinger/ |
| mips_opcode.h | 229 #define OP_AND 044
|
| /sdk/emulator/qtools/ |
| opcode.h | 15 OP_AND,
|
| armdis.cpp | 55 case OP_AND:
863 return OP_AND;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 229 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
480 case OP_AND:
615 case OP_AND:
|
| nv50_ir_lowering_nvc0.cpp | 677 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
687 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
912 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 229 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
480 case OP_AND:
615 case OP_AND:
|
| nv50_ir_lowering_nvc0.cpp | 677 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
687 bld.mkOp2(OP_AND, TYPE_U32, tmp[0], tmp[1],
912 bld.mkOp2(OP_AND, TYPE_U32, face, face, bld.mkImm(0x80000000));
[all...] |
| /external/chromium_org/base/test/ |
| trace_event_analyzer.h | 434 OP_AND,
508 return operator_ != OP_INVALID && operator_ < OP_AND;
|
| trace_event_analyzer.cc | 273 case OP_AND:
573 return Query(*this, rhs, OP_AND);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
415 case OP_AND:
|
| nv50_ir_lowering_nv50.cpp | 908 bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
929 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff));
931 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000));
|
| nv50_ir_peephole.cpp | 466 case OP_AND:
756 i->op = OP_AND;
1118 if ((logop->op == OP_AND || logop->op == OP_OR) &&
1137 operation redOp = (logop->op == OP_AND ? OP_SET_AND :
[all...] |
| nv50_ir_emit_nv50.cpp | 1284 assert(i->op == OP_AND);
1293 case OP_AND: code[1] = 0x04000000; break;
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
415 case OP_AND:
|
| nv50_ir_lowering_nv50.cpp | 908 bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
929 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff));
931 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000));
|
| nv50_ir_peephole.cpp | 466 case OP_AND:
756 i->op = OP_AND;
1118 if ((logop->op == OP_AND || logop->op == OP_OR) &&
1137 operation redOp = (logop->op == OP_AND ? OP_SET_AND :
[all...] |
| nv50_ir_emit_nv50.cpp | 1284 assert(i->op == OP_AND);
1293 case OP_AND: code[1] = 0x04000000; break;
[all...] |
