| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 379 case SM4_OPCODE_EQ: return OP_SET;
384 case SM4_OPCODE_GE: return OP_SET;
387 case SM4_OPCODE_IEQ: return OP_SET;
388 case SM4_OPCODE_IGE: return OP_SET;
389 case SM4_OPCODE_ILT: return OP_SET;
394 case SM4_OPCODE_INE: return OP_SET;
403 case SM4_OPCODE_LT: return OP_SET;
410 case SM4_OPCODE_NE: return OP_SET;
432 case SM4_OPCODE_ULT: return OP_SET;
433 case SM4_OPCODE_UGE: return OP_SET;
[all...] |
| nv50_ir_peephole.cpp | 157 if (insn->op != OP_SET && insn->op != OP_SLCT)
186 if (insn->op == OP_SET)
296 while (insn && insn->op != OP_SET) {
743 bld.mkCmp(OP_SET, CC_LT, TYPE_S32, tA, i->getSrc(0), bld.mkImm(0));
761 case OP_SET: // TODO: SET_AND,OR,XOR
767 if (imm0.reg.data.u32 != 0 || !si || si->op != OP_SET)
1130 if (set1->op != OP_SET) {
1134 if (set1->op != OP_SET)
1141 if (set0->op != OP_SET &&
[all...] |
| nv50_ir_lowering_nv50.cpp | 171 i->op == OP_SET)
436 bld.mkCmp(OP_SET, CC_GE, TYPE_U32, (s = bld.getSSA()), m, b);
817 i->op = OP_SET;
1021 bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, cdst, bld.loadImm(NULL, 0), pred);
1054 case OP_SET:
|
| nv50_ir_target_nv50.cpp | 99 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
427 case OP_SET:
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir.h | 77 OP_SET,
|
| nv50_ir_emit_nv50.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 379 case SM4_OPCODE_EQ: return OP_SET;
384 case SM4_OPCODE_GE: return OP_SET;
387 case SM4_OPCODE_IEQ: return OP_SET;
388 case SM4_OPCODE_IGE: return OP_SET;
389 case SM4_OPCODE_ILT: return OP_SET;
394 case SM4_OPCODE_INE: return OP_SET;
403 case SM4_OPCODE_LT: return OP_SET;
410 case SM4_OPCODE_NE: return OP_SET;
432 case SM4_OPCODE_ULT: return OP_SET;
433 case SM4_OPCODE_UGE: return OP_SET;
[all...] |
| nv50_ir_peephole.cpp | 157 if (insn->op != OP_SET && insn->op != OP_SLCT)
186 if (insn->op == OP_SET)
296 while (insn && insn->op != OP_SET) {
743 bld.mkCmp(OP_SET, CC_LT, TYPE_S32, tA, i->getSrc(0), bld.mkImm(0));
761 case OP_SET: // TODO: SET_AND,OR,XOR
767 if (imm0.reg.data.u32 != 0 || !si || si->op != OP_SET)
1130 if (set1->op != OP_SET) {
1134 if (set1->op != OP_SET)
1141 if (set0->op != OP_SET &&
[all...] |
| nv50_ir_lowering_nv50.cpp | 171 i->op == OP_SET)
436 bld.mkCmp(OP_SET, CC_GE, TYPE_U32, (s = bld.getSSA()), m, b);
817 i->op = OP_SET;
1021 bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, cdst, bld.loadImm(NULL, 0), pred);
1054 case OP_SET:
|
| nv50_ir_target_nv50.cpp | 99 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
427 case OP_SET:
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir.h | 77 OP_SET,
|
| nv50_ir_emit_nv50.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 234 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
596 case OP_SET:
623 case OP_SET:
|
| nv50_ir_lowering_nvc0.cpp | 493 i->op == OP_SET)
1041 bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, pdst, bld.mkImm(0), pred);
[all...] |
| nv50_ir_emit_nvc0.cpp | 893 if (i->op != OP_SET)
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 234 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
596 case OP_SET:
623 case OP_SET:
|
| nv50_ir_lowering_nvc0.cpp | 493 i->op == OP_SET)
1041 bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, pdst, bld.mkImm(0), pred);
[all...] |
| nv50_ir_emit_nvc0.cpp | 893 if (i->op != OP_SET)
[all...] |
