| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 74 i[7] = bld->mkOp2(OP_SHL, fTy, t[2], t[1], bld->mkImm(halfSize * 8));
306 if (i->op != OP_SHL || i->src(0).getFile() != FILE_GPR)
322 if (i->op == OP_SHL && i->src(0).getFile() == FILE_GPR)
343 if (i->op == OP_SHL && i->src(1).getFile() == FILE_IMMEDIATE)
348 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0));
|
| nv50_ir_peephole.cpp | 475 case OP_SHL:
652 i->op = OP_SHL;
790 case OP_SHL:
796 if (!si || si->op != OP_SHL)
[all...] |
| nv50_ir_target_nv50.cpp | 97 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
|
| nv50_ir_from_sm4.cpp | 396 case SM4_OPCODE_ISHL: return OP_SHL;
[all...] |
| nv50_ir.h | 65 OP_SHL,
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 74 i[7] = bld->mkOp2(OP_SHL, fTy, t[2], t[1], bld->mkImm(halfSize * 8));
306 if (i->op != OP_SHL || i->src(0).getFile() != FILE_GPR)
322 if (i->op == OP_SHL && i->src(0).getFile() == FILE_GPR)
343 if (i->op == OP_SHL && i->src(1).getFile() == FILE_IMMEDIATE)
348 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0));
|
| nv50_ir_peephole.cpp | 475 case OP_SHL:
652 i->op = OP_SHL;
790 case OP_SHL:
796 if (!si || si->op != OP_SHL)
[all...] |
| nv50_ir_target_nv50.cpp | 97 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
|
| nv50_ir_from_sm4.cpp | 396 case SM4_OPCODE_ISHL: return OP_SHL;
[all...] |
| nv50_ir.h | 65 OP_SHL,
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 232 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
625 case OP_SHL:
|
| nv50_ir_lowering_nvc0.cpp | 675 bld.mkOp2(OP_SHL, TYPE_U32, tmp[0], rRel, shCnt);
685 bld.mkOp2(OP_SHL, TYPE_U32, tmp[0], sRel, shCnt);
[all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 232 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
625 case OP_SHL:
|
| nv50_ir_lowering_nvc0.cpp | 675 bld.mkOp2(OP_SHL, TYPE_U32, tmp[0], rRel, shCnt);
685 bld.mkOp2(OP_SHL, TYPE_U32, tmp[0], sRel, shCnt);
[all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
| /external/qemu/target-i386/ |
| translate.c | 142 OP_SHL,
[all...] |
