| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
120 unsigned NumOps = Outs.size()
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
|
| HexagonCallingConvLower.h | 84 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| HexagonISelLowering.h | 90 SmallVectorImpl<ISD::OutputArg> &Outs,
134 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| HexagonISelLowering.cpp | 303 const SmallVectorImpl<ISD::OutputArg> &Outs,
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
386 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
432 Outs, OutVals, Ins, DAG);
460 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 107 const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SparcISelLowering.cpp | 165 const SmallVectorImpl<ISD::OutputArg> &Outs,
169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
239 const SmallVectorImpl<ISD::OutputArg> &Outs,
250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
673 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 131 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MSP430ISelLowering.cpp | 282 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
300 Outs, OutVals, Ins, dl, DAG, InVals);
410 const SmallVectorImpl<ISD::OutputArg> &Outs,
418 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
426 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
465 &Outs,
475 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
524 ISD::ArgFlagsTy Flags = Outs[i].Flags;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 555 const SmallVectorImpl<ISD::OutputArg> &Outs,
561 const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
611 const SmallVectorImpl<ISD::OutputArg> &Outs,
619 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 252 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
264 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
418 const SmallVectorImpl<ISD::OutputArg> &Outs,
424 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 250 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
261 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 159 const SmallVectorImpl<ISD::OutputArg> &Outs,
186 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 123 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 74 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
346 const SmallVectorImpl<ISD::OutputArg> &Outs,
417 if (Outs[OIdx].Flags.isByVal() == false) {
429 // update the index for Outs
437 assert((getValueType(Ty) == Outs[OIdx].VT ||
438 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
458 unsigned align = Outs[OIdx].Flags.getByValAlign();
496 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
521 // Args.size() and Outs.size() need not match
[all...] |
| NVPTXISelLowering.h | 130 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 527 const SmallVectorImpl<ISD::OutputArg> &Outs,
534 const SmallVectorImpl<ISD::OutputArg> &Outs,
540 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| A15SDOptimizer.cpp | 115 SmallVectorImpl<MachineInstr*> &Outs);
368 SmallVectorImpl<MachineInstr*> &Outs) {
402 Outs.push_back(MI);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.h | 57 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 66 SmallVector<ISD::OutputArg, 4> Outs;
67 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
70 Outs, Fn->getContext());
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 818 const SmallVectorImpl<ISD::OutputArg> &Outs,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 170 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
