| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 71 /// REG_SEQUENCE - This variadic instruction is used to form a register that
75 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
78 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
81 REG_SEQUENCE = 12,
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| /external/llvm/lib/Target/R600/ |
| R600OptimizeVectorRegisters.cpp | 63 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
325 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
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| AMDGPUIndirectAddressing.cpp | 283 TII->get(AMDGPU::REG_SEQUENCE),
292 // We only need to use REG_SEQUENCE for explicit defs, since the
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| SIISelLowering.cpp | 295 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
300 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
719 case AMDGPU::REG_SEQUENCE:
720 // Operand 0 is the register class id for REG_SEQUENCE instructions.
[all...] |
| AMDGPUISelDAGToDAG.cpp | 291 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
313 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 657 return getOpcode() == TargetOpcode::REG_SEQUENCE;
693 case TargetOpcode::REG_SEQUENCE:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 267 case TargetOpcode::REG_SEQUENCE:
307 case TargetOpcode::REG_SEQUENCE:
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| InstrEmitter.cpp | 588 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
596 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
600 "REG_SEQUENCE must have an odd number of operands!");
713 // Handle REG_SEQUENCE specially.
714 if (Opc == TargetOpcode::REG_SEQUENCE) {
[all...] |
| ScheduleDAGRRList.cpp | 297 if (Opcode == TargetOpcode::REG_SEQUENCE) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 56 case TargetOpcode::REG_SEQUENCE:
108 case TargetOpcode::REG_SEQUENCE:
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| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 338 // INSERT_SUBREG or REG_SEQUENCE.
465 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
475 TII->get(TargetOpcode::REG_SEQUENCE), Out)
587 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
608 // * REG_SEQUENCE: * If all except one of the input operands are
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| ARMISelDAGToDAG.cpp | 235 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 437 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
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