| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 685 #define REG_USE1 (1 << kRegUse1)
702 #define REG_USE01 (REG_USE0 | REG_USE1)
704 #define REG_USE12 (REG_USE1 | REG_USE2)
706 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
[all...] |
| CodegenCommon.cpp | 186 if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
245 if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
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| Assemble.cpp | [all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 529 #define REG_USE1 (1 << kRegUse1)
546 #define REG_USE01 (REG_USE0 | REG_USE1)
549 #define REG_USE12 (REG_USE1 | REG_USE2)
553 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
|
| CodegenCommon.cpp | 204 if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
253 if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
|
| GlobalOptimizations.cpp | 168 if ((flags & REG_USE1) &&
|
| Assemble.cpp | 148 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
[all...] |
| /art/compiler/dex/quick/ |
| local_optimizations.cc | 93 ((target_flags & (REG_USE0 | REG_USE1 | REG_USE2)) ==
94 (REG_USE0 | REG_USE1 | REG_USE2)) || // Skip wide stores.
|
| mir_to_lir-inl.h | 181 if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
|
| mir_to_lir.h | 59 #define REG_USE1 (1ULL << kRegUse1)
82 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
89 #define REG_USE01 (REG_USE0 | REG_USE1)
91 #define REG_USE12 (REG_USE1 | REG_USE2)
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 39 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \
51 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \
67 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \
144 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },
156 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },
168 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | [all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 152 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
[all...] |
