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    Searched refs:RecVec (Results 1 - 7 of 7) sorted by null

  /external/llvm/utils/TableGen/
CodeGenSchedule.h 30 typedef std::vector<Record*> RecVec;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
185 RecVec ItinDefList;
189 RecVec ItinRWDefs;
192 RecVec WriteResDefs
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SetTheory.h 65 typedef std::vector<Record*> RecVec;
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
CodeGenSchedule.cpp 140 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
183 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
190 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
196 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
199 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
216 RecVec SWDefs, SRDefs;
222 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
233 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
236 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
248 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW")
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SetTheory.cpp 26 typedef SetTheory::RecVec RecVec;
219 if (const RecVec *Result = ST.expand(Rec))
273 if (const RecVec *Result = expand(Def->getDef()))
296 const RecVec *SetTheory::expand(Record *Set) {
310 RecVec &EltVec = Expansions[Set];
SubtargetEmitter.cpp 90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
639 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
780 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
787 RecVec SubResources;
812 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
907 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
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RegisterInfoEmitter.cpp     [all...]
CodeGenRegisters.cpp 684 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
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