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  /external/llvm/lib/Target/R600/
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
31 Reserved.set(AMDGPU::ZERO);
32 Reserved.set(AMDGPU::HALF);
33 Reserved.set(AMDGPU::ONE);
34 Reserved.set(AMDGPU::ONE_INT);
35 Reserved.set(AMDGPU::NEG_HALF);
36 Reserved.set(AMDGPU::NEG_ONE);
37 Reserved.set(AMDGPU::PV_X);
38 Reserved.set(AMDGPU::ALU_LITERAL_X);
39 Reserved.set(AMDGPU::ALU_CONST)
    [all...]
SIRegisterInfo.cpp 27 BitVector Reserved(getNumRegs());
28 return Reserved;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
40 Reserved.set(AMDGPU::PREDICATE_BIT)
    [all...]
SIRegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
30 return Reserved;
  /external/mesa3d/src/gallium/drivers/radeon/
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
40 Reserved.set(AMDGPU::PREDICATE_BIT)
    [all...]
SIRegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
30 return Reserved;
  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 117 BitVector Reserved(getNumRegs());
121 Reserved.set(ReservedGPR32[I]);
124 Reserved.set(ReservedGPR64[I]);
130 Reserved.set(*Reg);
135 Reserved.set(*Reg);
140 Reserved.set(Mips::S0);
142 Reserved.set(Mips::FP);
143 Reserved.set(Mips::FP_64);
148 Reserved.set(Mips::HWR29);
149 Reserved.set(Mips::HWR29_64)
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 48 BitVector Reserved(getNumRegs());
49 // FIXME: G1 reserved for now for large imm generation by frame code.
50 Reserved.set(SP::G1);
54 Reserved.set(SP::G2);
55 Reserved.set(SP::G3);
56 Reserved.set(SP::G4);
58 // G5 is not reserved in 64 bit mode.
60 Reserved.set(SP::G5);
62 Reserved.set(SP::O6);
63 Reserved.set(SP::I6)
    [all...]
  /development/tools/recovery_l10n/
Android.mk 1 # Copyright 2012 Google Inc. All Rights Reserved.
  /development/tools/yuv420sp2rgb/
Android.mk 1 # Copyright 2005 Google Inc. All Rights Reserved.
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.cpp 62 BitVector Reserved(getNumRegs());
65 Reserved.set(AArch64::XSP);
66 Reserved.set(AArch64::WSP);
68 Reserved.set(AArch64::XZR);
69 Reserved.set(AArch64::WZR);
72 Reserved.set(AArch64::X29);
73 Reserved.set(AArch64::W29);
76 return Reserved;
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 39 BitVector Reserved(getNumRegs());
44 Reserved.set(SystemZ::R11D);
45 Reserved.set(SystemZ::R11W);
46 Reserved.set(SystemZ::R10Q);
50 Reserved.set(SystemZ::R15D);
51 Reserved.set(SystemZ::R15W);
52 Reserved.set(SystemZ::R14Q);
53 return Reserved;
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 77 BitVector Reserved(getNumRegs());
80 // Mark 4 special registers with subregisters as reserved.
81 Reserved.set(MSP430::PCB);
82 Reserved.set(MSP430::SPB);
83 Reserved.set(MSP430::SRB);
84 Reserved.set(MSP430::CGB);
85 Reserved.set(MSP430::PCW);
86 Reserved.set(MSP430::SPW);
87 Reserved.set(MSP430::SRW);
88 Reserved.set(MSP430::CGW)
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.cpp 74 BitVector Reserved(getNumRegs());
75 Reserved.set(HEXAGON_RESERVED_REG_1);
76 Reserved.set(HEXAGON_RESERVED_REG_2);
77 Reserved.set(Hexagon::R29);
78 Reserved.set(Hexagon::R30);
79 Reserved.set(Hexagon::R31);
80 Reserved.set(Hexagon::D14);
81 Reserved.set(Hexagon::D15);
82 Reserved.set(Hexagon::LC0);
83 Reserved.set(Hexagon::LC1)
    [all...]
  /external/chromium_org/third_party/icu/source/test/testdata/
tstfiles.mk 1 # Copyright (C) 2007, International Business Machines Corporation and others. All Rights Reserved.
  /external/icu4c/data/mappings/
ucmlocal.mk 1 # Copyright 2008 Google Inc. All Rights Reserved.
  /external/icu4c/test/testdata/
tstfiles.mk 1 # Copyright (C) 2007, International Business Machines Corporation and others. All Rights Reserved.
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 73 BitVector Reserved(getNumRegs());
76 Reserved.set(XCore::CP);
77 Reserved.set(XCore::DP);
78 Reserved.set(XCore::SP);
79 Reserved.set(XCore::LR);
81 Reserved.set(XCore::R10);
83 return Reserved;
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 141 BitVector Reserved(getNumRegs());
147 Reserved.set(PPC::ZERO);
148 Reserved.set(PPC::ZERO8);
152 Reserved.set(PPC::FP);
153 Reserved.set(PPC::FP8);
157 Reserved.set(PPC::BP);
158 Reserved.set(PPC::BP8);
160 // The counter registers must be reserved so that counter-based loops can
162 Reserved.set(PPC::CTR);
163 Reserved.set(PPC::CTR8)
    [all...]
  /external/freetype/src/sfnt/
ttmtx.c 135 FT_FRAME_SHORT ( Reserved[0] ),
136 FT_FRAME_SHORT ( Reserved[1] ),
137 FT_FRAME_SHORT ( Reserved[2] ),
138 FT_FRAME_SHORT ( Reserved[3] ),
  /external/libppp/src/
chap.h 5 * All rights reserved.
68 char Reserved[8];
  /external/llvm/lib/CodeGen/
RegisterClassInfo.cpp 11 // information about target register classes. Callee saved and reserved
63 // Different reserved registers?
65 if (Reserved.size() != RR.size() || RR != Reserved) {
67 Reserved = RR;
75 /// compute - Compute the preferred allocation order for RC with reserved
81 // Raw register count, including all reserved regs.
98 // Remove reserved registers from the allocation order.
99 if (Reserved.test(PhysReg))
151 /// nonoverlapping reserved registers. However, computing the allocation orde
    [all...]
  /development/tools/etc1tool/
Android.mk 1 # Copyright 2009 Google Inc. All Rights Reserved.
  /external/chromium_org/third_party/icu/source/test/perf/unisetperf/draft/
contperf.bat 2 rem others. All Rights Reserved.
span16perf.bat 2 rem others. All Rights Reserved.

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