| /external/llvm/lib/CodeGen/ |
| LiveDebugVariables.h | 40 /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
43 /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub-
45 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| PeepholeOptimizer.cpp | 150 unsigned SrcReg, DstReg, SubIdx;
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
165 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
172 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
173 // SrcReg:SubIdx should be replaced.
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
205 // Only accept uses of SrcReg:SubIdx.
206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
286 .addReg(DstReg, 0, SubIdx);
287 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set
[all...] |
| ExpandPostRAPseudos.cpp | 87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
88 unsigned SubIdx = MI->getOperand(3).getImm();
90 assert(SubIdx != 0 && "Invalid index for insert_subreg");
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
113 MI->RemoveOperand(3); // SubIdx
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| TargetRegisterInfo.cpp | 47 if (SubIdx) {
49 OS << ':' << TRI->getSubRegIndexName(SubIdx);
51 OS << ":sub(" << SubIdx << ')';
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| MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
121 if (!SubIdx)
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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| RegisterCoalescer.cpp | 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
335 "Cannot have a physical SubIdx");
[all...] |
| MachineRegisterInfo.cpp | 82 if (unsigned SubIdx = I.getOperand().getSubReg()) {
85 SubIdx);
87 NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx);
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| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 35 unsigned DestReg, unsigned SubIdx, int Val,
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| Thumb2RegisterInfo.cpp | 37 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
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| Thumb1RegisterInfo.h | 41 unsigned DestReg, unsigned SubIdx, int Val,
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| ARMBaseRegisterInfo.h | 164 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 336 const char *getSubRegIndexName(unsigned SubIdx) const {
337 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
339 return SubRegIndexNames[SubIdx-1];
343 /// register that are covered by SubIdx.
361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
362 // SubIdx == 0 is allowed, it has the lane mask ~0u.
363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
364 return SubRegIndexLaneMasks[SubIdx];
456 /// Reg so its sub-register of index SubIdx is Reg
[all...] |
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 315 // registers have a SubIdx sub-register.
317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
318 return SubClassWithSubReg.lookup(SubIdx);
321 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
323 SubClassWithSubReg[SubIdx] = SubRC;
327 // containing only SubIdx super-registers of this class.
328 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
331 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
333 SuperRegClasses[SubIdx].insert(SuperRC);
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| CodeGenRegisters.cpp | 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
481 if (!SubIdx)
484 NewIdx->addComposite(SI->first, SubIdx);
506 // Topological signature computed from SubIdx, TopoId(SubReg).
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 424 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
427 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
429 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
434 // VReg has been adjusted. It can be used with SubIdx operands now.
440 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
441 assert(RC && "No legal register class for VT supports that SubIdx");
475 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
484 SubIdx == DefSubIdx &&
496 // VReg may not support a SubIdx sub-register, and we may need to
499 VReg = ConstrainForSubReg(VReg, SubIdx,
[all...] |
| InstrEmitter.h | 85 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
87 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 159 while (unsigned SubIdx = *SubIndices++) {
161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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| AMDGPUInstrInfo.cpp | 39 unsigned &SubIdx) const {
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| AMDGPUInstrInfo.h | 54 unsigned &DstReg, unsigned &SubIdx) const;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 88 unsigned &SubIdx) const {
95 SubIdx = PPC::sub_32;
494 unsigned SubIdx;
498 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
499 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
500 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
501 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
502 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
503 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
504 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break
[all...] |
| PPCInstrInfo.h | 99 unsigned &SubIdx) const;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 38 unsigned &SubIdx) const {
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| AMDGPUInstrInfo.h | 52 unsigned &DstReg, unsigned &SubIdx) const;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 38 unsigned &SubIdx) const {
|
