| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 198 unsigned SubReg = *SubRegs;
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs;
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg = *SubRegs
[all...] |
| MachineInstrBundle.cpp | 175 unsigned SubReg = *SubRegs;
176 if (LocalDefSet.insert(SubReg))
177 LocalDefs.push_back(SubReg);
|
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
44 if (*Subs == SubReg)
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| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 224 const char *const *SubRegIndexNames; // Names of subreg indexes.
496 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
501 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
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| /external/llvm/lib/Target/R600/ |
| R600OptimizeVectorRegisters.cpp | 12 /// common data and/or have enough undef subreg using swizzle abilities.
187 unsigned SubReg = (*It).first;
194 .addReg(SubReg)
196 UpdatedRegToChan[SubReg] = Chan;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 108 // Return true if any CC result of MI would reflect the value of subreg
109 // SubReg of Reg.
110 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) {
115 MI->getOperand(0).getSubReg() == SubReg)
132 MI->getOperand(1).getSubReg() == SubReg)
|
| SystemZISelLowering.h | 221 bool ClearEven, unsigned SubReg) const;
|
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 65 unsigned SubReg = 0) const {
75 SubReg,
|
| MachineOperand.h | 69 /// MO_Register has no subReg.
339 void setSubReg(unsigned subReg) {
341 SubReg_TargetFlags = subReg;
342 assert(SubReg_TargetFlags == subReg && "SubReg out of range");
346 /// subregister Reg:SubReg. Take any existing SubReg index into account,
347 /// using TargetRegisterInfo to compose the subreg indices if necessary.
353 /// Reg, taking any existing SubReg into account. For instance,
564 unsigned SubReg = 0
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| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
438 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 448 /// EmitSubregNode - Generate machine code for subreg nodes.
609 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
610 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
699 // Handle subreg insert/extract specially
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| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 535 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
537 O << ARMInstPrinter::getRegisterName(SubReg);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 257 // Expand any composed subreg indices.
259 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
260 // expanded subreg indices recursively.
275 // Add I->second as a name for the subreg SRI->second, assuming it is
288 // Consider this subreg sequence:
299 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
311 // Compute the inverse SubReg -> Idx map.
429 const CodeGenRegister *SubReg = I->second;
430 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs
[all...] |
