| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
46 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 /// and punpckh*. VT indicates the type of the vector allowing it to handle
54 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
57 /// and punpckl*. VT indicates the type of the vector allowing it to handle
59 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm
[all...] |
| X86ShuffleDecode.cpp | 64 void DecodePALIGNRMask(MVT VT, unsigned Imm,
66 unsigned NumElts = VT.getVectorNumElements();
67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
69 unsigned NumLanes = VT.getSizeInBits() / 128;
83 /// VT indicates the type of the vector allowing it to handle different
85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
86 unsigned NumElts = VT.getVectorNumElements();
88 unsigned NumLanes = VT.getSizeInBits() / 128;
101 void DecodePSHUFHWMask(MVT VT, unsigned Imm,
103 unsigned NumElts = VT.getVectorNumElements()
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| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 103 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
105 setOperationAction(ISD::ADD, VT, Expand);
106 setOperationAction(ISD::AND, VT, Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
109 setOperationAction(ISD::MUL, VT, Expand);
110 setOperationAction(ISD::OR, VT, Expand);
111 setOperationAction(ISD::SHL, VT, Expand);
112 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::SRL, VT, Expand)
[all...] |
| SIRegisterInfo.h | 43 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| SIISelLowering.h | 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL,
46 bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const;
56 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
57 virtual MVT getScalarShiftAmountTy(EVT VT) const;
66 unsigned Reg, EVT VT) const;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| SIRegisterInfo.cpp | 53 MVT VT) const
55 switch(VT.SimpleTy) {
|
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, DL, 7)
[all...] |
| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| R600RegisterInfo.h | 47 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| SIRegisterInfo.cpp | 53 MVT VT) const
55 switch(VT.SimpleTy) {
|
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, DL, 7)
[all...] |
| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 176 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
208 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
244 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
245 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
257 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
258 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
264 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
265 return RepRegClassCostForVT[VT.SimpleTy];
271 bool isTypeLegal(EVT VT) const {
272 assert(!VT.isSimple() |
[all...] |
| /libcore/luni/src/main/java/java/util/ |
| EnumMap.java | 51 private static class Entry<KT extends Enum<KT>, VT> extends
52 MapEntry<KT, VT> {
53 private final EnumMap<KT, VT> enumMap;
57 Entry(KT theKey, VT theValue, EnumMap<KT, VT> em) {
71 Map.Entry<KT, VT> entry = (Map.Entry<KT, VT>) object;
102 public VT getValue() {
104 return (VT) enumMap.values[ordinal];
109 public VT setValue(VT value)
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString() << '\n'
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 25 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
35 EVT VT) const {
39 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
40 if (VT == MVT::Untyped)
44 return TargetLowering::getRepRegClassFor(VT);
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 349 SDVTList getVTList(EVT VT);
358 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
359 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
360 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
362 SDValue getTargetConstant(uint64_t Val, EVT VT) {
363 return getConstant(Val, VT, true);
365 SDValue getTargetConstant(const APInt &Val, EVT VT) {
366 return getConstant(Val, VT, true);
368 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
369 return getConstant(Val, VT, true)
[all...] |
| ValueTypes.h | 423 /// Return true if this has more bits than VT.
424 bool bitsGT(MVT VT) const {
425 return getSizeInBits() > VT.getSizeInBits();
428 /// Return true if this has no less bits than VT.
429 bool bitsGE(MVT VT) const {
430 return getSizeInBits() >= VT.getSizeInBits();
433 /// Return true if this has less bits than VT.
434 bool bitsLT(MVT VT) const {
435 return getSizeInBits() < VT.getSizeInBits();
438 /// Return true if this has no more bits than VT
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 95 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
96 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
117 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
119 if (VT != MVT::f32 && VT != MVT::f64)
126 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
132 (VT == MVT::f32) ? 4 : 8, Align);
141 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
245 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
247 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 VT.getVectorNumElements()/Factor);
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
336 /// legalization or if the specified VT is legal.
337 bool isTypeLegal(const EVT &VT) {
339 return TLI.isTypeLegal(VT);
344 EVT getSetCCResultType(EVT VT) const {
345 return TLI.getSetCCResultType(*DAG.getContext(), VT);
587 EVT VT = N0.getValueType();
592 DAG.FoldConstantArithmetic(Opc, VT,
595 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode)
[all...] |
| SelectionDAG.cpp | 78 bool ConstantFPSDNode::isValueValidForType(EVT VT,
80 assert(VT.isFloatingPoint() && "Can only convert between FP types");
85 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
669 EVT VT = cast<VTSDNode>(N)->getVT();
670 if (VT.isExtended()) {
671 Erased = ExtendedValueTypeNodes.erase(VT);
673 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
674 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
789 EVT VT = N->getValueType(0);
791 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &
[all...] |
