| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 32 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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| R600MCCodeEmitter.cpp | 51 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
170 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| SIMCCodeEmitter.cpp | 61 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
169 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 48 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
114 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
126 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
127 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
135 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
136 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
144 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
145 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
146 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
154 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUCodeEmitter.h | 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUCodeEmitter.h | 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 68 /// getMachineOpValue - Return binary encoding of operand. If the machine
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
113 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
136 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
148 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
159 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
172 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
176 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
190 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60 unsigned getMachineOpValue(const MachineInstr &MI,
187 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
203 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
216 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
234 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
238 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
250 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
254 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
273 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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| SIMCCodeEmitter.cpp | 77 /// getMachineOpValue - Reutrn the encoding for an MCOperand.
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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| R600MCCodeEmitter.cpp | 56 /// getMachineOpValue - Reutrn the encoding for an MCOperand.
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
620 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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| SIMCCodeEmitter.cpp | 77 /// getMachineOpValue - Reutrn the encoding for an MCOperand.
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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| R600MCCodeEmitter.cpp | 56 /// getMachineOpValue - Reutrn the encoding for an MCOperand.
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
620 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 152 /// getMachineOpValue - Return binary encoding of operand. If the machine
154 unsigned getMachineOpValue(const MachineInstr &MI,
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
162 // operand values, instead querying getMachineOpValue() directly for
471 /// getMachineOpValue - Return binary encoding of operand. If the machine
473 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
756 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
771 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
794 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 82 // getMachineOpValue - Return binary encoding of operand. If the machin
84 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
376 /// getMachineOpValue - Return binary encoding of operand. If the machine
379 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
403 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
404 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
413 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
424 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
425 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
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| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 99 /// getMachineOpValue - Return binary encoding of operand. If the machine
101 unsigned getMachineOpValue(const MachineInstr &MI,
200 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
201 return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
207 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
213 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +
214 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
217 /// getMachineOpValue - Return binary encoding of operand. If the machine
219 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 87 /// getMachineOpValue - Return binary encoding of operand. If the machine
89 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
353 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 72 /// getMachineOpValue - Return binary encoding of operand. If the machine
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
416 /// getMachineOpValue - Return binary encoding of operand. If the machine
419 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
[all...] |
