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  /external/llvm/test/MC/MachO/
bad-macro.s 5 .macro test_macro reg1, reg2
  /external/pixman/pixman/
pixman-arm-simd-asm.S 223 .macro src_0565_8888_2pixels, reg1, reg2
225 bic WK&reg2, WK&reg1, MASK @ RRRRR000000BBBBBrrrrr000000bbbbb
227 mov WK&reg1, WK&reg2, lsl #16 @ rrrrr000000bbbbb0000000000000000
229 bic WK&reg2, WK&reg2, WK&reg1, lsr #16 @ RRRRR000000BBBBB0000000000000000
231 orr WK&reg2, WK&reg2, WK&reg2, lsr #5 @ RRRRRRRRRR0BBBBBBBBBB00000000000
235 pkhtb WK&reg2, WK&reg2, WK&reg2, asr #5 @ RRRRRRRR--------BBBBBBBB-------
    [all...]
pixman-region.c 295 PREFIX (_equal) (region_type_t *reg1, region_type_t *reg2)
301 if (reg1->extents.x1 != reg2->extents.x1)
304 if (reg1->extents.x2 != reg2->extents.x2)
307 if (reg1->extents.y1 != reg2->extents.y1)
310 if (reg1->extents.y2 != reg2->extents.y2)
313 if (PIXREGION_NUMRECTS (reg1) != PIXREGION_NUMRECTS (reg2))
317 rects2 = PIXREGION_RECTS (reg2);
750 region_type_t * reg2, /* 2d region in operation */
784 if (PIXREGION_NAR (reg1) || PIXREGION_NAR (reg2))
799 numRects = PIXREGION_NUMRECTS (reg2);
    [all...]
pixman-arm-neon-asm.h 84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits variable
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]!
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]!
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]! variable
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]! variable
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]! variable
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&] variable
256 .macro pixld2_s elem_size, reg1, reg2, mem_operand variable
276 pixld1_s elem_size, reg2, mem_operand variable
    [all...]
  /dalvik/vm/compiler/codegen/arm/
ArchFactory.cpp 74 int reg1, int reg2, int dOffset,
78 res = opRegReg(cUnit, kOpCmp, reg1, reg2);
  /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/
x86gas.pl 70 { my($addr,$reg1,$reg2,$idx)=@_;
78 $reg2 = "%$reg2" if ($reg2);
82 if ($reg2)
84 $ret .= "($reg1,$reg2,$idx)";
x86nasm.pl 36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
57 if ($reg2 ne "")
59 $ret .= "$reg2*$idx";
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
56 if ($reg2 ne "")
58 $ret .= "$reg2*$idx";
  /external/openssl/crypto/perlasm/
x86gas.pl 70 { my($addr,$reg1,$reg2,$idx)=@_;
78 $reg2 = "%$reg2" if ($reg2);
82 if ($reg2)
84 $ret .= "($reg1,$reg2,$idx)";
x86nasm.pl 36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
57 if ($reg2 ne "")
59 $ret .= "$reg2*$idx";
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
56 if ($reg2 ne "")
58 $ret .= "$reg2*$idx";
  /external/v8/src/
regexp-macro-assembler-tracer.h 62 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
regexp-macro-assembler-tracer.cc 300 int reg2,
302 PrintF(" CheckNotRegistersEqual(reg1=%d, reg2=%d, label[%08x]);\n",
304 reg2,
306 assembler_->CheckNotRegistersEqual(reg1, reg2, on_not_equal);
regexp-macro-assembler-irregexp.h 99 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /dalvik/vm/compiler/codegen/x86/libenc/
enc_wrapper.h 186 int reg2, bool isPhysical2, LowOpndRegType type, char* stream);
230 int reg, bool isPhysical, int reg2,
233 int reg, bool isPhysical, int reg2,
  /external/valgrind/main/none/tests/s390x/
cksm.c 26 register uint64_t reg2 asm("2") = (uint64_t) buff;
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
37 addr = reg2;
  /art/compiler/dex/quick/x86/
codegen_x86.h 50 bool SameRegType(int reg1, int reg2);
67 void FlushRegWide(int reg1, int reg2);
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
184 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
185 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
target_x86.cc 104 bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
105 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
316 void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
318 RegisterInfo* info2 = GetRegInfo(reg2);
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_fragshader.c 49 GLuint reg2 = 0; local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT;
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT;
109 SET_INST_2(opnum, optype) |= reg2;
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 49 GLuint reg2 = 0; local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT;
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT;
109 SET_INST_2(opnum, optype) |= reg2;
  /dalvik/vm/compiler/codegen/x86/
LowerHelper.cpp 322 int reg, int reg2, LowOpndRegType type) {
325 reg-reg2, size==OpndSize_64, stream);
328 stream = encoder_reg_reg(m, size, reg, true, reg2, true, type, stream);
338 int reg2, bool isPhysical2, LowOpndRegType type) {
339 return lower_reg_reg(m, ATOM_NORMAL, size, reg, reg2, type);
352 int reg2, bool isPhysical2, LowOpndRegType type) {
356 if(isMnemonicMove(m) && regAll == reg2) return NULL;
357 return lower_reg_reg(m, ATOM_NORMAL, size, regAll, reg2, type);
359 stream = encoder_reg_reg(m, size, reg, isPhysical, reg2, isPhysical2, type, stream);
368 int reg2, bool isPhysical2, LowOpndRegType type)
    [all...]
Lower.h 646 int reg2, bool isPhysical2);
648 int reg2, bool isPhysical2);
652 int reg2, bool isPhysical2);
656 int reg2, bool isPhysical2);
701 int reg2, bool isPhysical2);
708 int reg2, bool isPhysical2);
710 int reg2, bool isPhysical2);
727 int reg2, bool isPhysical2);
741 int reg2, bool isPhysical2);
744 int reg2, bool isPhysical2)
    [all...]
  /art/compiler/dex/quick/mips/
codegen_mips.h 50 bool SameRegType(int reg1, int reg2);
67 void FlushRegWide(int reg1, int reg2);
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);

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