| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 178 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
183 { ISD::SHL, MVT::v8i32, 1 },
184 { ISD::SRL, MVT::v8i32, 1 },
185 { ISD::SRA, MVT::v8i32, 1 },
204 { ISD::SDIV, MVT::v8i32, 8*20 },
208 { ISD::UDIV, MVT::v8i32, 8*20 },
300 { ISD::MUL, MVT::v8i32, 4 },
301 { ISD::SUB, MVT::v8i32, 4 },
302 { ISD::ADD, MVT::v8i32, 4 },
405 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 85 v8i32 = 34, // 8 x i32 enumerator in enum:llvm::MVT::SimpleValueType
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
283 case v8i32:
319 case v8i32:
397 case v8i32:
512 if (NumElements == 8) return MVT::v8i32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 221 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
222 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
232 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
252 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
405 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
|
| ARMISelLowering.cpp | 568 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
569 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 98 DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
196 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask);
269 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 152 case MVT::v8i32: return "v8i32";
215 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 93 case MVT::v8i32: return "MVT::v8i32";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 57 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
[all...] |
