| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGCall.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringChecker.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngine.cpp | 425 ExplodedNodeSet Dst;
431 Dst.insert(DstI);
435 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
511 ExplodedNodeSet Dst;
512 NodeBuilder Bldr(Tmp, Dst, *currBldrCtx);
519 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
524 ExplodedNodeSet Dst;
527 ProcessAutomaticObjDtor(D.castAs<CFGAutomaticObjDtor>(), Pred, Dst);
530 ProcessBaseDtor(D.castAs<CFGBaseDtor>(), Pred, Dst);
533 ProcessMemberDtor(D.castAs<CFGMemberDtor>(), Pred, Dst);
[all...] |
| BugReporter.cpp | 585 const CFGBlock *Dst = BE->getDst();
622 if (const Stmt *S = Dst->getLabel()) {
694 if (*(Src->succ_begin()+1) == Dst)
722 if (*(Src->succ_begin()+1) == Dst) {
742 if (*(Src->succ_begin()+1) == Dst) {
763 if (*(Src->succ_begin()) == Dst) {
791 if (*(Src->succ_begin()+1) == Dst) {
821 if (*(Src->succ_begin()+1) == Dst)
[all...] |
| /external/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | 190 return Src->mayReadFromMemory() && Dst->mayReadFromMemory();
196 return Src->mayWriteToMemory() && Dst->mayWriteToMemory();
202 return Src->mayWriteToMemory() && Dst->mayReadFromMemory();
208 return Src->mayReadFromMemory() && Dst->mayWriteToMemory();
660 // Examines the loop nesting of the Src and Dst
677 // ... - loops containing Src but not Dst
678 // SrcLevels - innermost loop containing Src but not Dst
679 // ... - loops containing Dst but not Src
680 // MaxLevels - innermost loops containing Dst but not Src
699 // to A (the Src) and the load from A (the Dst), we'll note that the
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 132 /// which are the src/dst of the copy instruction CopyMI. This returns
217 unsigned &Src, unsigned &Dst,
220 Dst = MI->getOperand(0).getReg();
225 Dst = MI->getOperand(0).getReg();
258 unsigned Src, Dst, SrcSub, DstSub;
259 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
263 // If one register is a physreg, it must be Dst.
265 if (TargetRegisterInfo::isPhysicalRegister(Dst))
267 std::swap(Src, Dst);
274 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| AddressSanitizer.cpp | 595 Value *Dst = MI->getDest();
613 instrumentMemIntrinsicParam(MI, Dst, Length, InsertBefore, true);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| ScalarReplAggregates.cpp | 730 // Noop transfer. Src == Dst
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 721 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
723 assert(Dst && Src && "Bad sub-register");
726 DstRegs.insert(Dst);
728 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 567 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
568 // => ext $dst, $src, size, pos
607 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
609 // => ins $dst, $src, size, pos, $src1
[all...] |
