/external/llvm/lib/CodeGen/ |
PrologEpilogInserter.cpp | 326 MachineBasicBlock* MBB = ReturnBlocks[ri]; 327 I = MBB->end(); --I; 332 while (I2 != MBB->begin() && (--I2)->isTerminator()) 335 bool AtStart = I == MBB->begin(); 342 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) { 346 TII.loadRegFromStackSlot(*MBB, I, Reg, 349 assert(I != MBB->begin() && 354 I = MBB->begin(); 369 MachineBasicBlock* MBB = BI->first; 383 I = MBB->begin() [all...] |
TargetInstrInfo.cpp | 59 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, 100 MachineBasicBlock *MBB = Tail->getParent(); 102 // Remove all the old successors of MBB from the CFG. 103 while (!MBB->succ_empty()) 104 MBB->removeSuccessor(MBB->succ_begin()); 106 // Remove all the dead instructions from the end of MBB. 107 MBB->erase(Tail, MBB->end()); 109 // If MBB isn't immediately before MBB, insert a branch to it [all...] |
EarlyIfConversion.cpp | 139 /// Return true if all non-terminator instructions in MBB can be safely 141 bool canSpeculateInstrs(MachineBasicBlock *MBB); 164 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted, 166 bool canConvertIf(MachineBasicBlock *MBB); 175 /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely 183 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { 186 if (!MBB->livein_empty()) { 187 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n"); 195 for (MachineBasicBlock::iterator I = MBB->begin(), 196 E = MBB->getFirstTerminator(); I != E; ++I) [all...] |
LiveDebugVariables.cpp | 87 bool dominates(MachineBasicBlock *MBB) { 90 if (LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB)) 128 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo. 129 void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, 470 MachineBasicBlock *MBB = MFI; 471 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end(); 478 SlotIndex Idx = MBBI == MBB->begin() ? 479 LIS->getMBBStartIdx(MBB) [all...] |
LiveIntervalAnalysis.cpp | 205 MachineBasicBlock *MBB = MBBI; 206 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()]; 208 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end(); 281 const MachineBasicBlock *MBB = MFI; 284 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty()) 288 SlotIndex Begin = Indexes->getMBBStartIdx(MBB); 289 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber()); 290 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin() [all...] |
MachineBasicBlock.cpp | 65 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) { 66 MBB.print(OS); 70 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the 71 /// parent pointer of the MBB, the MBB numbering, and any instructions in the 72 /// MBB to be on the right operand list for registers. 74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it 75 /// gets the next available unique MBB number. If it is removed from a 128 /// MBB list to another, we need to update the parent pointers and the use/de [all...] |
RegAllocFast.cpp | 63 MachineBasicBlock *MBB; 290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); 304 if (MI == MBB->end()) { 310 MachineBasicBlock *MBB = DBG->getParent(); 312 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE)) 626 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI); 783 DEBUG(dbgs() << "\nAllocating " << *MBB); 788 MachineBasicBlock::iterator MII = MBB->begin(); 791 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 792 E = MBB->livein_end(); I != E; ++I [all...] |
ShrinkWrapping.cpp | 126 bool PEI::isReturnBlock(MachineBasicBlock* MBB) { 127 return (MBB && !MBB->empty() && MBB->back().isReturn()); 197 /// for the given MBB by looking forward in the MCFG at MBB's 200 bool PEI::calcAnticInOut(MachineBasicBlock* MBB) { 203 // AnticOut[MBB] = INTERSECT(AnticIn[S] for S in SUCCESSORS(MBB)) 205 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin() [all...] |
SplitKit.cpp | 62 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num); 63 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor(); 65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB); 70 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator(); 71 if (FirstTerm == MBB->end()) 81 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin(); 96 // Find the value leaving MBB. 101 // If the value leaving MBB was defined after the call in MBB, it can' [all...] |
StrongPHIElimination.cpp | 217 static MachineOperand *findLastUse(MachineBasicBlock *MBB, unsigned Reg) { 220 for (MachineBasicBlock::reverse_iterator RI = MBB->rbegin(); ; ++RI) { 221 assert (RI != MBB->rend()); 370 MachineBasicBlock *MBB = I->first; 378 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 379 SE = MBB->succ_end(); SI != SE; ++SI) { 389 MachineOperand *LastUse = findLastUse(MBB, SrcReg); 392 SrcLI.removeRange(LastUseIndex.getRegSlot(), LI->getMBBEndIdx(MBB)); 520 MachineBasicBlock &MBB, 525 std::vector<MachineInstr*> &DefInstrs = PHISrcDefs[&MBB]; [all...] |
TailDuplication.cpp | 115 bool TailDuplicateAndUpdate(MachineBasicBlock *MBB, 119 void RemoveDeadBlock(MachineBasicBlock *MBB); 149 MachineBasicBlock *MBB = I; 150 SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(), 151 MBB->pred_end()); 152 MachineBasicBlock::iterator MI = MBB->begin(); 153 while (MI != MBB->end()) { 168 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI; 178 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() 185 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FrameLowering.cpp | 50 MachineBasicBlock &MBB = MF.front(); 51 MachineBasicBlock::iterator MBBI = MBB.begin(); 54 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes, 96 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) 109 for (; MBBI != MBB.end(); ++MBBI) { 120 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP, 133 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) 149 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes, 164 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL) [all...] |
AArch64InstrInfo.cpp | 41 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg) 55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg) 62 BuildMI(MBB, I, DL, get(AArch64::MSRix)) 68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg) 80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg) 85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg) 98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP) 103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg) 113 BuildMI(MBB, I, DL, get(Opc), DestReg [all...] |
/external/llvm/lib/Target/ARM/ |
A15SDOptimizer.cpp | 70 unsigned createDupLane(MachineBasicBlock &MBB, 76 unsigned createExtractSubreg(MachineBasicBlock &MBB, 82 unsigned createVExt(MachineBasicBlock &MBB, 87 unsigned createRegSequence(MachineBasicBlock &MBB, 92 unsigned createInsertSubreg(MachineBasicBlock &MBB, 97 unsigned createImplicitDef(MachineBasicBlock &MBB, 431 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB, 437 AddDefaultPred(BuildMI(MBB, 450 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB, 456 BuildMI(MBB, [all...] |
ARMBaseRegisterInfo.cpp | 385 emitLoadConstPool(MachineBasicBlock &MBB, 391 MachineFunction &MF = *MBB.getParent(); 398 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 562 materializeFrameBaseRegister(MachineBasicBlock *MBB, 565 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 569 MachineBasicBlock::iterator Ins = MBB->begin(); 571 if (Ins != MBB->end()) 574 const MachineFunction &MF = *MBB->getParent(); 575 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 580 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg [all...] |
ARMExpandPseudoInsts.cpp | 56 bool ExpandMI(MachineBasicBlock &MBB, 58 bool ExpandMBB(MachineBasicBlock &MBB); 64 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 376 MachineBasicBlock &MBB = *MI.getParent(); 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 441 MachineBasicBlock &MBB = *MI.getParent(); 448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 492 MachineBasicBlock &MBB = *MI.getParent(); 500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 582 MachineBasicBlock &MBB = *MI.getParent() [all...] |
ARMFrameLowering.cpp | 120 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 125 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 128 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 133 MachineBasicBlock &MBB = MF.front(); 134 MachineBasicBlock::iterator MBBI = MBB.begin(); 148 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 164 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 169 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 225 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 267 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes [all...] |
/external/llvm/lib/Target/Mips/ |
MipsDelaySlotFiller.cpp | 93 /// Set bits in Uses corresponding to MBB's live-out registers except for 95 void addLiveOut(const MachineBasicBlock &MBB, 200 bool runOnMachineBasicBlock(MachineBasicBlock &MBB); 211 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 217 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const; 219 /// This function searches MBB in the forward direction for an instruction 221 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const; 223 /// This function searches one of MBB's successor blocks for an instruction 226 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const; 228 /// Pick a successor block of MBB. Return NULL if MBB doesn't have [all...] |
MipsSEFrameLowering.cpp | 42 bool expandInstr(MachineBasicBlock &MBB, Iter I); 43 void expandLoadCCond(MachineBasicBlock &MBB, Iter I); 44 void expandStoreCCond(MachineBasicBlock &MBB, Iter I); 45 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); 46 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); 47 bool expandCopy(MachineBasicBlock &MBB, Iter I); 48 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst, 70 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { 74 expandLoadCCond(MBB, I); 78 expandStoreCCond(MBB, I) [all...] |
MipsSEInstrInfo.cpp | 91 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 113 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 132 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 165 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 178 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 183 if (I != MBB.end()) DL = I->getDebugLoc(); 184 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 213 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 217 if (I != MBB.end()) DL = I->getDebugLoc() [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 253 MachineBasicBlock &MBB = *MI.getParent(); 255 MachineFunction &MF = *MBB.getParent(); 286 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 290 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 294 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 311 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 316 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 322 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 326 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 336 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg [all...] |
/external/llvm/lib/Target/R600/ |
R600ControlFlowFinalizer.cpp | 147 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I) 154 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) { 167 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), 203 MachineBasicBlock *MBB = InsertPos->getParent(); 207 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(), 216 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I) 221 for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) { 252 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(), 338 MachineBasicBlock &MBB = *MB [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineOperand.h | 152 MachineBasicBlock *MBB; // For MO_MachineBasicBlock. 419 return Contents.MBB; 506 void setMBB(MachineBasicBlock *MBB) { 508 Contents.MBB = MBB; 583 static MachineOperand CreateMBB(MachineBasicBlock *MBB, 586 Op.setMBB(MBB);
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SlotIndexes.h | 349 /// MBBRanges - Map MBB number to (start, stop) indexes. 353 /// and MBB id. 392 void repairIndexesInRange(MachineBasicBlock *MBB, 443 const MachineBasicBlock *MBB = MI->getParent(); 444 assert(MBB && "MI must be inserted inna basic block"); 445 MachineBasicBlock::const_iterator I = MI, B = MBB->begin(); 448 return getMBBStartIdx(MBB); 460 const MachineBasicBlock *MBB = MI->getParent(); 461 assert(MBB && "MI must be inserted inna basic block"); 462 MachineBasicBlock::const_iterator I = MI, E = MBB->end() [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 172 /// CaseBB - The MBB in which to emit the compare and branch 226 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {} 233 /// MBB - the MBB into which to emit the code for the indirect jump. 234 MachineBasicBlock *MBB; 235 /// Default - the MBB of the default bb, which is a successor of the range 236 /// check MBB. This is when updating PHI nodes in successors. 413 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
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