| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 951 // Because there are S+1 ones in the replicated mask, an immediate of all
961 // First we have to make sure the mask is actually repeated in each slot for
1055 uint64_t Mask = (1ULL << Num1s) - 1;
1058 Mask = (Mask >> Rotation)
1059 | ((Mask << (Width - Rotation)) & WidthMask);
1061 Imm = Mask;
1063 Mask <<= Width;
1064 Imm |= Mask;
1076 // If the value is 0 when we mask out all the bits that could be set wit
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 685 // Into: MTCRF mask, %R3 ;; cr7
688 unsigned Mask = 0x80 >> OutContext.getRegisterInfo()
693 .addImm(Mask)
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 40 unsigned int Mask;
113 && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
128 unsigned int mask)
134 sc_data.Mask = mask;
674 unsigned int mask)
677 if (rc_src_reads_dst_mask(file, mask, index,
689 unsigned int mask)
693 (mask & d->Writer->WriteMask)) {
|
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| ValueTracking.cpp | 94 APInt Mask = APInt::getLowBitsSet(BitWidth, LHSKnownZeroOut);
95 KnownZero |= KnownZero2 & Mask;
96 KnownOne |= KnownOne2 & Mask;
105 APInt Mask = APInt::getLowBitsSet(BitWidth, RHSKnownZeroOut);
106 KnownZero |= LHSKnownZero & Mask;
107 KnownOne |= LHSKnownOne & Mask;
243 "V, Mask, KnownOne and KnownZero should have same BitWidth");
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 395 // Instead, we load all significant words, mask bits off, and concatenate
579 SDValue Mask = Op.getOperand(0);
583 assert(VT.isVector() && !Mask.getValueType().isVector()
599 // Generate a mask operand.
603 && "Invalid mask size");
605 // What is the size of each element in the vector mask.
608 Mask = DAG.getSelect(DL, BitTy, Mask,
612 // Broadcast the mask so that the entire vector is all-one or all zero.
613 SmallVector<SDValue, 8> Ops(NumElem, Mask);
[all...] |
| SelectionDAGBuilder.h | 150 uint64_t Mask;
155 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
157 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
254 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
255 uint64_t Mask;
|
| LegalizeFloatTypes.cpp | 145 // Mask = ~(1 << (Size-1))
148 SDValue Mask = DAG.getConstant(API, NVT);
150 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
210 SDValue Mask = DAG.getNode(ISD::SHL, dl, LVT, DAG.getConstant(1, LVT),
213 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, LVT));
214 LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
[all...] |
| TargetLowering.cpp | 348 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
359 "Mask size mismatches value type size!");
720 // Handle the sign bit, adjusted to where it is now in the mask.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 86 // This should return a register mask that is the same as that returned by
678 unsigned Mask = (1 << NumBits) - 1;
679 if ((unsigned)Offset <= Mask * Scale)
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 291 /// elements from either LHS or RHS, return the shuffle mask and true.
294 SmallVectorImpl<Constant*> &Mask) {
300 Mask.assign(NumElts, UndefValue::get(Type::getInt32Ty(V->getContext())));
306 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), i));
312 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()),
330 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
331 // If so, update the mask to reflect the inserted undef.
332 Mask[InsertedIdx] = UndefValue::get(Type::getInt32Ty(V->getContext()));
345 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
346 // If so, update the mask to reflect the inserted value
[all...] |
| InstCombineAddSub.cpp | 956 APInt Mask = APInt::getHighBitsSet(TySizeBits, ExtendAmt);
957 if (!MaskedValueIsZero(XorLHS, Mask))
[all...] |
| InstCombineCasts.cpp | 373 APInt Mask = APInt::getHighBitsSet(OrigBitWidth, OrigBitWidth-BitWidth);
374 if (MaskedValueIsZero(I->getOperand(0), Mask) &&
375 MaskedValueIsZero(I->getOperand(1), Mask)) {
612 // Mask off any bits that are set and won't be shifted away.
[all...] |
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 448 Constant *Mask = ConstantVector::get(Idxs);
450 Value *V = new ShuffleVectorInst(Val0, Val1, Mask, "Shuff",
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.h | 176 unsigned char Mask;
|
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineVerifier.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 714 unsigned Mask = 1;
716 if (ErrorInfo & Mask) {
718 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
720 Mask <<= 1;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 95 // Return a mask with Count low bits set.
104 // (or (rotl Input, Rotate), ~Mask)
108 // (and (rotl Input, Rotate), Mask)
114 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
119 uint64_t Mask;
247 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
249 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask);
597 // We need a constant mask.
622 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) {
625 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.h | 176 unsigned char Mask;
|
| /external/clang/lib/Basic/ |
| SourceManager.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/include/llvm/IR/ |
| Instructions.h | [all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 63 // instructions that for the IT block. Firstcond and Mask correspond to the
65 void setITState(char Firstcond, char Mask) {
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
4704 unsigned mask = fieldFromInstruction(Insn, 0, 4); local
[all...] |
