| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
389 /// ReverseBranchCondition - Return the inverse opcode of the
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| XCoreRegisterInfo.cpp | 188 llvm_unreachable("Unexpected Opcode");
209 llvm_unreachable("Unexpected Opcode");
237 llvm_unreachable("Unexpected Opcode");
252 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
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| XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
122 int Opcode;
124 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
128 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
225 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 36 /// The opcode of the instruction, as used in an MCInst
42 /// The opcode field from the record; this is the opcode used in the Intel
44 uint8_t Opcode;
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
|
| radeon_program.h | 65 rc_presubtract_op Opcode;
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8;
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| /external/mesa3d/src/mesa/main/ |
| atifragshader.h | 24 GLenum opcode; member in struct:ati_fs_opcode_st
53 GLenum Opcode[2];
62 GLenum Opcode;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_program.h | 65 rc_presubtract_op Opcode;
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 297 struct match_info Opcode;
334 tokens.Opcode.String = inst_str + matches[1].rm_so;
335 tokens.Opcode.Length = match_length(matches, 1);
347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) {
350 inst->U.I.Opcode = info->Opcode;
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| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
155 MCInst() : Opcode(0) {}
157 void setOpcode(unsigned Op) { Opcode = Op; }
158 unsigned getOpcode() const { return Opcode; }
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| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 64 /// opcode and an optional sequence of operands.
67 Instruction(uint8_t Opcode)
68 : Opcode(Opcode)
71 uint8_t Opcode;
77 /// Convenience methods to add a new instruction with the given opcode and
79 void addInstruction(uint8_t Opcode) {
80 Instructions.push_back(Instruction(Opcode));
83 void addInstruction(uint8_t Opcode, uint64_t Operand1) {
84 Instructions.push_back(Instruction(Opcode));
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 186 const char *Instruction::getOpcodeName(unsigned OpCode) {
187 switch (OpCode) {
277 // We have two instructions of identical opcode and #operands. Check to see
345 // We have two instructions of identical opcode and #operands. Check to see
476 bool Instruction::isAssociative(unsigned Opcode) {
477 return Opcode == And || Opcode == Or || Opcode == Xor ||
478 Opcode == Add || Opcode == Mul
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 190 unsigned Opcode = MCID.getOpcode();
191 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
198 static bool isFpMulInstruction(unsigned Opcode) {
199 switch (Opcode) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 337 unsigned Opcode = 0;
340 Opcode = MSP430::MOV8rm_POST;
343 Opcode = MSP430::MOV16rm_POST;
349 return CurDAG->getMachineNode(Opcode, SDLoc(N),
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 53 unsigned Opcode = Mips::Mflo16;
54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
58 unsigned Opcode = Mips::Mfhi16;
59 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
239 unsigned Opcode = Node->getOpcode();
249 switch(Opcode) {
261 if (Opcode == ISD::ADDE) {
290 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
304 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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| MipsSEISelDAGToDAG.cpp | 318 unsigned Opcode = Node->getOpcode();
327 switch(Opcode) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 214 unsigned Opcode;
256 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
257 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
258 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
259 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
260 case Intrinsic::rint: Opcode = ISD::FRINT; break;
261 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
295 Opcode = ISD::FSQRT; break;
299 Opcode = ISD::FFLOOR; break;
303 Opcode = ISD::FNEARBYINT; break
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 322 int Opcode = SU->getInstr()->getOpcode();
324 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
327 if (TII->isALUInstr(Opcode)) {
331 switch (Opcode) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 169 unsigned Opcode = MI->getOpcode();
171 if (Opcode == SystemZ::AHI)
173 else if (Opcode == SystemZ::AGHI)
216 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
217 if (!Opcode)
220 MI->setDesc(TII->get(Opcode));
234 int Opcode = MI->getOpcode();
235 const MCInstrDesc &Desc = TII->get(Opcode);
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| SystemZFrameLowering.cpp | 290 unsigned Opcode;
293 Opcode = SystemZ::AGHI;
295 Opcode = SystemZ::AGFI;
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
429 unsigned Opcode = MBBI->getOpcode();
430 if (Opcode != SystemZ::LMG)
436 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
445 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 44 const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) {
46 return MII->getName(Opcode);
250 uint32_t Opcode = mcInst.getOpcode();
257 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
258 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
259 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
260 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 237 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
253 Inst.setOpcode(Opcode);
287 unsigned Opcode) {
332 Inst.setOpcode(Opcode);
415 default: llvm_unreachable("Invalid opcode");
439 default: llvm_unreachable("Invalid opcode");
454 unsigned Opcode = OutMI.getOpcode();
457 OutMI.setOpcode(Opcode);
473 unsigned Opcode;
475 default: llvm_unreachable("Invalid opcode");
[all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 289 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
290 switch (Opcode) {
452 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
454 switch (Opcode) {
681 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
682 switch (Opcode) {
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 231 unsigned Opcode = J->getOpcode();
232 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
233 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
234 bool UseSignedOp = Opcode == Instruction::SDiv ||
235 Opcode == Instruction::SRem;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 297 struct match_info Opcode;
334 tokens.Opcode.String = inst_str + matches[1].rm_so;
335 tokens.Opcode.Length = match_length(matches, 1);
347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) {
350 inst->U.I.Opcode = info->Opcode;
|
