| /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| emit-rtl.h | 41 /* Set the attributes for MEM appropriate for a spill slot. */
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| /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/ |
| emit-rtl.h | 41 /* Set the attributes for MEM appropriate for a spill slot. */
|
| /art/compiler/dex/quick/x86/ |
| call_x86.cc | 237 /* Spill core callee saves */
239 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
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| /art/runtime/arch/arm/ |
| portable_entrypoints_arm.S | 30 push {r0, r4, r5, r9, r11, lr} @ spill regs
61 pop {r0, r4, r5, r9, r11, lr} @ restore spill regs
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| /external/llvm/docs/CommandGuide/ |
| lli.rst | 187 **-disable-spill-fusing**
189 Disable fusing of spill code into instructions.
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| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
205 /// as currently those new intervals are not guaranteed to spill.
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| MachineFrameInfo.h | 71 /// example, register allocator spill code never needs variable sized
100 // isSpillSlot - If true the stack object is used as spill slot. It
485 /// to a spill slot..
507 /// represents a spill slot, returning a nonnegative identifier to represent
550 /// Before the PrologueEpilogueInserter has placed the CSR spill code, this
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| /external/llvm/test/CodeGen/PowerPC/ |
| sjlj.ll | 73 ; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
138 ; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
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| /external/llvm/test/CodeGen/SystemZ/ |
| frame-09.ll | 41 ; This function should require all GPRs but no other spill slots.
111 ; emergency spill slots at 160(%r11), so create a frame of size 524192
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| /external/llvm/test/CodeGen/X86/ |
| pr1505b.ll | 40 ; Spill returned value:
48 ; Spill returned value:
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| /external/valgrind/main/docs/internals/ |
| register-uses.txt | 80 r30 y altivec spill temporary
190 r30 y altivec spill temporary
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| /external/chromium_org/v8/src/ia32/ |
| lithium-gap-resolver-ia32.cc | 257 // 3. Prefer to spill a register that is not used in any remaining move
297 // Spill on demand to use a temporary register for memory-to-memory
433 // spill on demand because the simple spill implementation cannot avoid
451 // Memory-memory. Spill on demand to use a temporary. If there is a
494 // Double-width memory-to-memory. Spill on demand to use a general
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| /external/llvm/lib/CodeGen/ |
| RegAllocPBQP.cpp | 14 // register assignment. If any variables are selected for spilling then spill
366 ++pregOpt; // +1 to account for spill option.
496 spiller->spill(LRE);
505 assert(!(*itr)->empty() && "Empty spill range.");
512 // We need another round if spill intervals were added.
565 // * Spill if necessary
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| SplitKit.h | 227 /// it to overlap the other intervals. If it is going to spill anyway, no
259 /// The current spill mode, selected by reset().
292 /// LiveRangeCalc instance for the complement interval when in spill mode.
295 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the
297 /// LRCalc instance. When not in spill mode, all intervals can share one.
333 /// way that minimizes code size. This implements the SM_Size spill mode.
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| RegAllocGreedy.cpp | 54 SplitSpillMode("split-spill-mode", cl::Hidden,
55 cl::desc("Spill mode for splitting live ranges"),
159 float MaxWeight; ///< Maximum spill weight evicted.
589 // Never evict spill products. They cannot split or spill.
593 // register for it. This is indicated by an infinite spill weight. These
693 // hints, and only evict smaller spill weights.
777 // Number of spill code instructions to insert.
800 // Accumulate the total frequency of inserted spill code.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 472 // If this is a thumb spill / restore, we will be using a constpool load to
506 /// saveScavengerRegister - Spill the register so it can be used by the
514 // Thumb1 can't use the emergency spill slot on the stack because
594 // means the stack pointer cannot be used to access the emergency spill slot
599 "Cannot use SP to access the emergency spill slot in "
602 "Cannot use SP to access the emergency spill slot in "
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| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 45 /// the spill instruction refers to an undefined register. This code needs
665 // For SVR4, don't emit a move for the CR spill slot if we haven't
672 // For 64-bit SVR4 when we have spilled CRs, the spill location
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| texturing.cpp | 387 CONTEXT_STORE(s.reg, generated_vars.texture[i].spill[0]);
388 CONTEXT_STORE(t.reg, generated_vars.texture[i].spill[1]);
411 // We don't have a way to spill registers automatically
412 // spill depth and AA regs, when we know we may have to.
413 // build the spill list...
437 Spill spill(registerFile(), *this, spill_list);
463 CONTEXT_LOAD(s.reg, generated_vars.texture[i].spill[0]);
464 CONTEXT_LOAD(t.reg, generated_vars.texture[i].spill[1]);
614 CONTEXT_STORE(s.reg, generated_vars.texture[i].spill[0])
[all...] |
| GGLAssembler.h | 124 class Spill
127 Spill(RegisterFile& regFile, ARMAssemblerInterface& gen, uint32_t reglist)
146 ~Spill() {
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| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 528 /// requirements, and there is no register class with a smaller spill size
589 /// legal to use in the current sub-target and has the same spill size.
682 /// frame pointer based accesses to spill to the scavenger emergency spill
701 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
704 /// reserved as its spill slot. This tells PEI not to create a new stack frame
764 /// saveScavengerRegister - Spill the register so it can be used by the
766 /// otherwise. If this function does not spill the register, the scavenger
767 /// will instead spill it to the emergency spill slot
[all...] |
| /dalvik/vm/compiler/codegen/x86/ |
| AnalysisO1.cpp | 216 //! this array says whether a spill location is used (0 means not used, 1 means used)
[all...] |
| /art/runtime/ |
| stack.h | 477 * spill or Method* in bytes using Method*.
487 * | core callee-save spill | {variable sized}
489 * | fp callee-save spill |
|
| /external/llvm/test/CodeGen/ARM/ |
| fast-isel-intrinsic.ll | 58 ; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
75 ; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
113 ; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
|
| /external/v8/src/ |
| lithium-allocator.h | 555 // Spill the given life range after position pos.
558 // Spill the given life range after position start and up to position end.
565 void Spill(LiveRange* range);
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| /external/valgrind/main/VEX/priv/ |
| host_generic_regs.h | 80 needed to spill each class of register. It allocates the following
261 /* Return insn(s) to spill/restore a real reg to a spill slot
|
