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  /packages/apps/Settings/res/values-nb/
arrays.xml 267 <item msgid="1097324338692486211">"spill inn lyd"</item>
268 <item msgid="5031552983987798163">"spill av lyd"</item>
312 <item msgid="1720492593061838172">"Spill inn lyd"</item>
313 <item msgid="3493046322001257041">"Spill av lyd"</item>
  /art/compiler/dex/quick/x86/
target_x86.cc 480 // Spill mask not including fake return address register
495 // Spill mask not including fake return address register
  /bionic/libc/arch-arm/generic/bionic/
memcpy.S 95 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
212 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
  /external/chromium_org/v8/src/
lithium.cc 268 // Local or spill slot. Skip the frame pointer, function, and
374 // spill slots.
  /external/llvm/lib/CodeGen/
VirtRegMap.cpp 14 // references by replacing them with physical register references - adding spill
41 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
  /external/llvm/lib/Target/ARM/
README-Thumb.txt 18 temporaries to spill values into.
186 These instructions preserve the condition code which is important if the spill
  /external/llvm/lib/Target/XCore/
XCoreFrameLowering.cpp 154 // R10 is live-in. It is killed at the spill.
255 // Add the callee-saved register as live-in. It's killed at the spill.
  /external/llvm/test/CodeGen/ARM/
struct-byval-frame-index.ll 3 ; Check a spill right after a function call with large struct byval is correctly
8 ; CHECK: str r{{.*}}, [sp, [[SLOT:#[0-9]+]]] @ 4-byte Spill
  /external/llvm/test/CodeGen/SystemZ/
frame-08.ll 6 ; It is big enough to require two emergency spill slots at 160(%r15),
74 ; It is big enough to require two emergency spill slots at 160(%r15),
bswap-02.ll 101 ; Test a case where we spill the source of at least one LRVR. We want
bswap-03.ll 101 ; Test a case where we spill the source of at least one LRVGR. We want
fp-conv-02.ll 73 ; Test a case where we spill the source of at least one LDEBR. We want
fp-conv-03.ll 91 ; Test a case where we spill the source of at least one LXEBR. We want
fp-conv-04.ll 91 ; Test a case where we spill the source of at least one LXDBR. We want
fp-sqrt-01.ll 75 ; Test a case where we spill the source of at least one SQEBR. We want
fp-sqrt-02.ll 75 ; Test a case where we spill the source of at least one SQDBR. We want
int-conv-09.ll 106 ; Test a case where we spill the source of at least one LGFR. We want
  /external/v8/src/
lithium.h 523 // Allocation index indexed arrays of spill slot operands for registers
524 // that are also in spill slots at an OSR entry. NULL for environments
  /external/valgrind/main/coregrind/
pub_core_threadstate.h 106 guest state area, its two shadows, and the spill area, are
118 /* Spill area. */
  /packages/apps/Dialer/res/values-nb/
strings.xml 40 <string name="notification_action_voicemail_play" msgid="6113133136977996863">"Spill av"</string>
107 <string name="description_call_log_play_button" msgid="651182125650429846">"Spill av talemelding"</string>
  /external/chromium_org/webkit/browser/blob/
blob_storage_controller.cc 110 // TODO(michaeln): Blob memory storage does not yet spill over to disk,
  /external/llvm/lib/Target/Mips/
Mips16FrameLowering.cpp 115 // It's killed at the spill, unless the register is RA and return address
MipsFrameLowering.cpp 121 // callee-saved spill.
  /external/llvm/lib/Target/SystemZ/
README.txt 210 We might want to model all access registers and use them to spill
  /external/llvm/lib/Target/X86/
README-FPStack.txt 64 folding spill code into the instructions.

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