| /external/llvm/test/CodeGen/SystemZ/ |
| int-conv-10.ll | 115 ; Test a case where we spill the source of at least one LLGFR. We want
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| frame-04.ll | 6 ; This function should require all FPRs, but no other spill slots.
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| frame-05.ll | 5 ; This function should require all GPRs, but no other spill slots. The caller
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| frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
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| int-conv-01.ll | 107 ; Test a case where we spill the source of at least one LBR. We want
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| int-conv-02.ll | 116 ; Test a case where we spill the source of at least one LLCR. We want
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| int-conv-03.ll | 107 ; Test a case where we spill the source of at least one LGBR. We want
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| int-conv-04.ll | 116 ; Test a case where we spill the source of at least one LLGCR. We want
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| /external/llvm/test/CodeGen/Thumb2/ |
| crash.ll | 53 ; Make sure the DPair register class can spill.
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| /external/llvm/test/CodeGen/X86/ |
| 2012-01-10-UndefExceptionEdge.ll | 11 ; so the return value can spill.
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| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 85 * | spill region | {variable sized}
168 rRET = 8, // fake return address register for core spill mask.
178 rRET = 16, // fake return address register for core spill mask.
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| /external/llvm/lib/CodeGen/ |
| SjLjEHPrepare.cpp | 285 /// edge and spill them.
341 DEBUG(dbgs() << "SJLJ Spill: " << *Inst << " around "
348 // If we decided we need a spill, do it.
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 307 // 2. The RC spill size must not be smaller than our spill size.
308 // 3. RC spill alignment must be compatible with ours.
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| /external/chromium/sdch/open-vcdiff/src/ |
| vcdecoder_test.cc | 91 // value to spill over into another byte. Luckily, this test data happens
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| /external/chromium_org/sdch/open-vcdiff/src/ |
| vcdecoder_test.cc | 91 // value to spill over into another byte. Luckily, this test data happens
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| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_fs.h | 175 uint32_t offset; /* spill/unspill offset */
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| brw_vec4.h | 190 uint32_t offset; /* spill/unspill offset */
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| /external/chromium_org/third_party/sqlite/src/test/ |
| attach2.test | 222 # is set too small, then changes will spill to the database, forcing
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| /external/chromium_org/v8/src/arm/ |
| lithium-gap-resolver-arm.cc | 101 // offsets (more than 1K or 4K) require us to spill this spilled value to
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| /external/chromium_org/v8/src/mips/ |
| lithium-gap-resolver-mips.cc | 102 // offsets (more than 1K or 4K) require us to spill this spilled value to
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| /external/chromium_org/v8/src/x64/ |
| regexp-macro-assembler-x64.h | 144 // stack (before the return address) to spill parameter registers. We
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| /external/chromium_org/webkit/browser/blob/ |
| blob_storage_context.cc | 163 // TODO(michaeln): Blob memory storage does not yet spill over to disk,
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 197 // Add the callee-saved register as live-in. It's killed at the spill.
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPrologEpilogPass.cpp | 182 // Then assign frame offsets to stack objects that are not used to spill
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 197 // possible because there aren't any unused spill slots.
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