| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 600 * and base and dest are the same, spill some other register to
|
| /dalvik/vm/native/ |
| java_lang_reflect_Field.cpp | 572 const s4* valuePtr = (s4*) &args[7]; /* 64-bit vars spill into args[8] */
|
| /external/chromium/chrome/browser/autocomplete/ |
| autocomplete_popup_view_mac.mm | 70 // actual border so that it can spill a glow into the toolbar or
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_vec4_emit.cpp | 820 /* Debug of register spilling: Go spill everything. */
|
| /external/chromium_org/third_party/npapi/npspy/extern/nspr/md/ |
| _solaris.h | 507 ** always has room for the registers to spill to...
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| /external/chromium_org/v8/src/ |
| objects-debug.cc | 1096 PrintF("\n JSObject Spill Statistics (#%d):\n", number_of_objects_);
[all...] |
| /external/jmonkeyengine/engine/src/core-plugins/com/jme3/texture/plugins/ |
| TGALoader.java | 476 // start at data[offsetBytes]... spill into next byte as needed.
|
| /external/libogg/src/ |
| framing.c | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveInterval.h | 429 /// span instructions. It doesn't pay to spill such an interval.
|
| Passes.h | 397 /// SpillPlacement analysis. Suggest optimal placement of spill code between
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 505 // We assume a single instruction only has a spill or reload, not
519 CommentOS << MMO->getSize() << "-byte Spill\n";
523 CommentOS << MMO->getSize() << "-byte Folded Spill\n";
526 // Check for spill-induced copies
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 370 // callee-save register for this purpose or allocate an extra spill slot.
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 196 // know how to spill them. If we make our prologue/epilogue code smarter at
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 12 // allocation, but because we have a spill in between the feeder and new value
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 399 // We don't want to spill/restore the counter register, and so we don't
|
| /external/llvm/lib/Target/X86/ |
| README.txt | 631 Leaf functions that require one 4-byte spill slot have a prolog like this:
759 This seems like a cross between remat and spill folding.
1052 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1212 enough to warrant the spill.
[all...] |
| X86RegisterInfo.td | 418 // values, though they really are f80 values. This will cause us to spill
|
| /external/llvm/test/CodeGen/Mips/ |
| ra-allocatable.ll | 96 ; CHECK: sw $ra, {{[0-9]+}}($sp) # 4-byte Folded Spill
|
| /external/llvm/test/CodeGen/X86/ |
| 2009-03-23-MultiUseSched.ll | 3 ; RUN: not grep spill %t
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_emit.cpp | 820 /* Debug of register spilling: Go spill everything. */
|
| /external/v8/src/ |
| flag-definitions.h | 542 "report heap spill statistics along with heap_stats "
|
| objects-debug.cc | 842 PrintF("\n JSObject Spill Statistics (#%d):\n", number_of_objects_);
|
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 609 generate spill/reload of 128-bit registers since current register
|
| /external/valgrind/main/memcheck/tests/ |
| wrap6.c | 20 /* to spill is quite difficult, requiring v > 28 or so. */ \
|
| /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| cfgloop.h | 648 /* The cost for register when we need to spill. */
|
