| /external/llvm/test/CodeGen/ARM/ |
| 2010-05-18-LocalAllocCrash.ll | 3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
|
| /external/llvm/lib/CodeGen/ |
| SpillPlacement.cpp | 1 //===-- SpillPlacement.cpp - Optimal Spill Code Placement -----------------===//
10 // This file implements the spill code placement analysis.
24 // The energy function represents the expected spill code execution frequency,
45 INITIALIZE_PASS_BEGIN(SpillPlacement, "spill-code-placement",
46 "Spill Code Placement Analysis", true, true)
49 INITIALIZE_PASS_END(SpillPlacement, "spill-code-placement",
50 "Spill Code Placement Analysis", true, true)
76 /// BiasN - Sum of blocks that prefer a spill.
101 /// mustSpill - Return True if this node is so biased that it must spill.
103 // We must spill if Bias < -sum(weights) or the MustSpill flag was set
[all...] |
| CalcSpillWeights.cpp | 29 "Calculate spill weights", false, false)
33 "Calculate spill weights", false, false)
45 DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
130 // Don't recompute spill weight for an unspillable register.
183 // Weakly boost the spill weight of hinted registers.
|
| InlineSpiller.cpp | 53 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
54 cl::desc("Disable inline spill hoisting"));
71 // Variables that are valid during spill(), but used by multiple methods.
77 // All registers to spill to StackSlot, including the main register.
91 // True when all reaching defs were reloads: No spill is necessary.
100 // The preferred register to spill.
156 void spill(LiveRangeEdit &);
204 // When spilling a virtual register, we also spill any snippets it is connected
210 // spill slots which can be important in tight loops.
235 // %Reg = COPY %snip / SPILL %snip, fi
1299 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 95 // Integer spill area is handled with "pop".
151 // Determine the sizes of each callee-save spill areas and record which frame
152 // belongs to which callee-save spill areas.
217 // For iOS, FP is R7, which has now been stored in spill area 1.
219 // into spill area 1, including the FP in R11. In either case, it is
234 // Determine starting offsets of spill areas.
385 // Move SP to start of FP callee save spill area.
541 // since it's available. This is handy for the emergency spill slot, in
727 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
729 /// pointer pointing to the d8 spill slot
[all...] |
| /dalvik/vm/mterp/x86/ |
| OP_CONST_CLASS.S | 29 SPILL(rIBASE)
|
| OP_CONST_STRING.S | 28 SPILL(rIBASE)
|
| OP_CONST_STRING_JUMBO.S | 28 SPILL(rIBASE)
|
| OP_DIV_LONG.S | 6 SPILL(rIBASE) # save rIBASE/%edx
|
| OP_DIV_LONG_2ADDR.S | 7 SPILL(rIBASE) # save rIBASE/%edx
|
| bindivLit16.S | 9 SPILL(rIBASE)
|
| header.S | 38 sub FrameSize,%esp # Allocate storage for spill, locals & outs
50 will also have an associated spill location (mostly useful for those assigned
82 /* Spill offsets relative to %ebp */
103 /* for spill region: increase size by 48 (to keep 16-byte alignment) */
111 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
|
| OP_CHECK_CAST.S | 41 SPILL(rIBASE)
71 SPILL(rIBASE)
|
| entry.S | 34 * for 9 spill slots, 4 local slots, 5 arg slots to bring
39 /* Spill callee save regs */
|
| /external/chromium_org/net/base/ |
| test_data_stream.cc | 58 // Consume data from the spill buffer.
|
| test_data_stream.h | 36 // Consume data from the spill buffer.
|
| /external/chromium_org/third_party/sqlite/src/test/ |
| tkt2409.test | 15 # obtain an EXCLUSIVE lock while trying to spill the cache during
23 # tkt-2409-1.*: Cause a cache-spill during an INSERT that is within
29 # an exclusive lock when attempting a cache-spill is no longer an
33 # tkt-2409-2.*: Cause a cache-spill while updating the change-counter
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-10-11-SpillDead.ll | 7 ; The call to @g forces a spill of that register.
|
| reghinting.ll | 4 ;; The registers %x and %y must both spill across the finit call.
|
| /art/runtime/entrypoints/quick/ |
| quick_trampoline_entrypoints.cc | 46 // | arg3 spill | | Caller's frame
47 // | arg2 spill | |
48 // | arg1 spill | |
66 // | arg3 spill | | Caller's frame
67 // | arg2 spill | |
68 // | arg1 spill | |
85 // | arg3 spill | | Caller's frame
86 // | arg2 spill | |
87 // | arg1 spill | |
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 1 //===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
64 return "Hexagon Expand Predicate Spill Code";
90 "Not a Frame Pointer, Nor a Spill Slot");
137 "Not a Frame Pointer, Nor a Spill Slot");
187 const char *Name = "Hexagon Expand Predicate Spill Code";
188 PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
|
| /art/compiler/jni/quick/x86/ |
| calling_convention_x86.cc | 94 // We spill the argument registers on X86 to free them up for scratch use, we then assume
130 // Plus return value spill area size
|
| /art/runtime/arch/arm/ |
| context_arm.cc | 51 // Lowest number spill is farthest away, walk registers and fill into context
61 // Lowest number spill is farthest away, walk registers and fill into context
|
| /art/runtime/arch/mips/ |
| context_mips.cc | 50 // Lowest number spill is farthest away, walk registers and fill into context.
60 // Lowest number spill is farthest away, walk registers and fill into context.
|
| /art/runtime/arch/x86/ |
| context_x86.cc | 45 // Lowest number spill is farthest away, walk registers and fill into context.
46 int j = 2; // Offset j to skip return address spill.
|
