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  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_fs_reg_allocate.cpp 233 /* Failed to allocate registers. Spill a reg, and the caller will
239 fail("no register to spill\n");
291 * spill. Nothing else will make it up to MRF 14/15.
311 * spill/unspill we'll have to do, and guess that the insides of
322 * registers have a width of 1 so if we try to spill them we'll
383 /* Generate spill/unspill instructions for the objects being
384 * spilled. Right now, we spill or unspill the whole thing to a
386 * could just spill/unspill the GRF being accessed.
brw_wm_pass2.c 166 /* Allocate a spill slot. Note that allocations start from 0x40 -
174 /* The spill will be done in brw_wm_emit.c immediately after the
188 * TODO: implement spill-to-reg so that we can rearrange discontigous
189 * free regs and then spill the oldest non-free regs in sequence.
303 * result registers. Where necessary spill registers to scratch space
  /external/chromium_org/v8/test/mjsunit/regress/
regress-crbug-173907.js 36 function spill() { function
45 spill(); // At this point initial values for phi1 and phi2 are spilled.
  /external/llvm/lib/CodeGen/
RegisterScavenging.cpp 13 // spill slots.
377 // have to spill. Search explicitly rather than masking out based on
389 // If we found an unused register there is no reason to spill it.
402 // We need to scavenge a register but have no spill slot, the target
411 // otherwise, use the emergency stack spill slot.
413 // Spill the scavenged register before I.
415 "Cannot scavenge register without an emergency spill slot!");
437 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
PrologEpilogInserter.cpp 91 // Scan the function for modified callee saved registers and insert spill code
95 // Determine placement of CSR spill/restore code:
266 // Nope, just spill it anywhere convenient.
278 // Spill it to the stack where we must.
288 /// insertCSRSpillsAndRestores - Insert spill and restore code for
308 // Spill using target interface.
313 // It's killed at the spill.
316 // Insert the spill to the stack frame.
388 // It's killed at the spill.
391 // Insert the spill to the stack frame
    [all...]
  /external/llvm/test/CodeGen/Mips/
stldst.ll 36 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
38 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_fs_reg_allocate.cpp 233 /* Failed to allocate registers. Spill a reg, and the caller will
239 fail("no register to spill\n");
291 * spill. Nothing else will make it up to MRF 14/15.
311 * spill/unspill we'll have to do, and guess that the insides of
322 * registers have a width of 1 so if we try to spill them we'll
383 /* Generate spill/unspill instructions for the objects being
384 * spilled. Right now, we spill or unspill the whole thing to a
386 * could just spill/unspill the GRF being accessed.
brw_wm_pass2.c 166 /* Allocate a spill slot. Note that allocations start from 0x40 -
174 /* The spill will be done in brw_wm_emit.c immediately after the
188 * TODO: implement spill-to-reg so that we can rearrange discontigous
189 * free regs and then spill the oldest non-free regs in sequence.
303 * result registers. Where necessary spill registers to scratch space
  /art/compiler/jni/quick/
calling_convention.h 187 // Registers to spill to caller's out registers on entry.
199 // | { Return value spill } | (live on return slow paths)
230 // Callee save registers to spill prior to native code (which may clobber)
233 // Spill mask values
  /dalvik/vm/mterp/x86/
OP_IGET.S 14 SPILL(rIBASE) # preserve rIBASE
OP_IGET_WIDE.S 12 SPILL(rIBASE) # preserve rIBASE
OP_IPUT.S 15 SPILL (rIBASE)
OP_IPUT_WIDE.S 12 SPILL(rIBASE)
  /external/llvm/test/CodeGen/ARM/
gpr-paired-spill-thumbinst.ll 17 ; Make sure we are actually creating the Thumb versions of the spill
  /external/llvm/test/CodeGen/Hexagon/
validate-offset.ll 5 ; by 'Hexagon Expand Predicate Spill Code' pass.
  /external/llvm/test/CodeGen/PowerPC/
buildvec_canonicalize.ll 12 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
frame-size.ll 10 ; Check that the RS spill slot has been allocated (because the estimate
  /external/llvm/test/CodeGen/Thumb/
2011-06-16-NoGPRs.ll 6 ; to spill them.
  /external/llvm/test/CodeGen/Thumb2/
inflate-regs.ll 7 ; RAGreedy should split the range and use d16-d31 to avoid a spill.
  /external/llvm/test/CodeGen/X86/
2008-01-08-SchedulerCrash.ll 3 ; Test scheduling a multi-use compare. We should neither spill flags
  /art/compiler/jni/quick/arm/
calling_convention_arm.cc 89 // We spill the argument registers on ARM to free them up for scratch use, we then assume
134 // Compute spill mask to agree with callee saves initialized in the constructor
149 // Plus return value spill area size
  /art/compiler/jni/quick/mips/
calling_convention_mips.cc 89 // We spill the argument registers on MIPS to free them up for scratch use, we then assume
137 // Compute spill mask to agree with callee saves initialized in the constructor
153 // Plus return value spill area size
  /external/llvm/include/llvm/CodeGen/
RegAllocPBQP.h 76 // spill is a preg. (This might be extended one day to support remat).
83 // We hardcode option zero as the spill option.
109 /// spill, interference and coalescing costs by default. You can extend this
  /external/llvm/lib/Target/PowerPC/
PPCMachineFunctionInfo.h 46 /// Does this function spill using instructions with only r+r (not r+i)
68 /// calls. Used for creating an area before the register spill area.
87 /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
  /external/chromium_org/v8/src/
lithium-allocator.h 541 // Spill the given life range after position pos.
544 // Spill the given life range after position [start] and up to position [end].
549 // Spill the given life range after position [start] and up to position [end].
558 // If we are trying to spill a range inside the loop try to
559 // hoist spill position out to the point just before the loop.
563 void Spill(LiveRange* range);

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