| /external/chromium_org/v8/src/mips/ |
| macro-assembler-mips.h | 576 DEFINE_INSTRUCTION(Addu);
625 Addu(sp, sp, Operand(-kPointerSize));
675 Addu(sp, sp, Operand(kPointerSize));
684 Addu(sp, sp, 2 * kPointerSize);
692 Addu(sp, sp, 3 * kPointerSize);
696 Addu(sp, sp, Operand(count * kPointerSize));
[all...] |
| constants-mips.cc | 260 case ADDU:
|
| /external/v8/src/mips/ |
| macro-assembler-mips.h | 567 DEFINE_INSTRUCTION(Addu);
617 Addu(sp, sp, Operand(-kPointerSize));
666 Addu(sp, sp, Operand(kPointerSize));
674 Addu(sp, sp, 2 * kPointerSize);
682 Addu(sp, sp, 3 * kPointerSize);
686 Addu(sp, sp, Operand(count * kPointerSize));
[all...] |
| constants-mips.cc | 256 case ADDU:
|
| /external/llvm/test/CodeGen/Mips/ |
| atomic.ll | 15 ; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4
23 ; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4
124 ; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
150 ; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
|
| dsp-r1.ll | 401 ; CHECK: addu.qb
405 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)
411 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
419 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)
425 declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
[all...] |
| dsp-patterns.ll | 79 ; R1: addu.qb ${{[0-9]+}}
|
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 84 /*32 */ "add", "addu", "sub", "subu", "and", "or ", "xor", "nor",
208 * "addu" is a "move" only in 32-bit mode. What's the correct
209 * answer - never decode addu/daddu as "move"?
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/alsa/ |
| iatomic.h | 731 " addu %0, %2 \n"
775 " addu %0, %1, %3 \n"
778 " addu %0, %1, %3 \n"
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/alsa/ |
| iatomic.h | 731 " addu %0, %2 \n"
775 " addu %0, %1, %3 \n"
778 " addu %0, %1, %3 \n"
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/alsa/ |
| iatomic.h | 731 " addu %0, %2 \n"
775 " addu %0, %1, %3 \n"
778 " addu %0, %1, %3 \n"
|
| /art/runtime/ |
| disassembler_mips.cc | 78 { kRTypeMask, 33, "addu", "DST", },
|
| /bionic/libc/kernel/arch-mips/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /external/llvm/lib/Target/Mips/ |
| MipsDSPInstrFormats.td | 33 // ADDU.QB sub-class format.
|
| MipsLongBranch.cpp | 279 // addu $at, $ra, $at
301 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
|
| MipsInstrInfo.td | [all...] |
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| uaccess.h | 30 #define __UA_ADDU "addu"
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 225 void Addu(Register rd, Register rs, Register rt);
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 23 # CHECK: addu $9, $6, $7
|
| mips32_le.txt | 23 # CHECK: addu $9, $6, $7
|
