| /external/llvm/test/CodeGen/Mips/ |
| setult.ll | 18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| setcc-se.ll | 16 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
109 ; CHECK: sltu ${{[0-9]+}}
142 ; CHECK: sltu ${{[0-9]+}}
|
| cmov.ll | 170 ; O32: sltu ${{[0-9]+}}
191 ; O32: sltu ${{[0-9]+}}
|
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.c | [all...] |
| MIPS32int.stdout.exp | [all...] |
| MIPS32int.stdout.exp-BE | [all...] |
| MIPS32int.stdout.exp-mips32 | [all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 346 COMPARE(sltu(a0, a1, a2),
347 "00a6202b sltu a0, a1, a2");
348 COMPARE(sltu(s0, s1, s2),
349 "0232802b sltu s0, s1, s2");
350 COMPARE(sltu(t2, t3, t4),
351 "016c502b sltu t2, t3, t4");
352 COMPARE(sltu(v0, v1, a2),
353 "0066102b sltu v0, v1, a2");
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 356 COMPARE(sltu(a0, a1, a2),
357 "00a6202b sltu a0, a1, a2");
358 COMPARE(sltu(s0, s1, s2),
359 "0232802b sltu s0, s1, s2");
360 COMPARE(sltu(t2, t3, t4),
361 "016c502b sltu t2, t3, t4");
362 COMPARE(sltu(v0, v1, a2),
363 "0066102b sltu v0, v1, a2");
|
| /dalvik/vm/mterp/mips/ |
| OP_CMP_LONG.S | 32 sltu t0, a0, a2 # compare lo
|
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 195 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
199 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
219 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
230 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
235 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
|
| MicroMipsInstrInfo.td | 26 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
|
| /external/kernel-headers/original/asm-mips/ |
| div64.h | 41 " sltu %5, %0, %z6\n\t" \
|
| /external/llvm/test/MC/Mips/ |
| micromips-alu-instructions.s | 22 # CHECK: sltu $3, $3, $5 # encoding: [0x90,0x1b,0xa3,0x00]
51 sltu $3, $3, $5
|
| mips-alu-instructions.s | 27 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
58 sltu $3, $3, $5
|
| mips64-alu-instructions.s | 25 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
53 sltu $3, $3, $5
|
| /art/compiler/dex/quick/mips/ |
| int_mips.cc | 37 * sltu t0, x.lo, y.lo
342 * sltu v1,v0,a2
362 * sltu t1,a0,a2
384 * sltu t1,r_zero
|
| /bionic/libc/kernel/arch-mips/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 78 DBG sltu $at,$t8,$v0
165 DBG sltu $at,$t8,$v0
|
