| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | 418 // op2 can be cmp or slt/sltu
605 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
627 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
998 // Purpose: b = Sltu rl, rr.
1002 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1053 // Purpose: b = Sltu rl, rr.
1057 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1146 // Format: SLTU rx, ry MIPS16e
1150 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1154 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
[all...] |
| MipsInstrInfo.td | [all...] |
| MipsSEISelDAGToDAG.cpp | 229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
|
| /system/core/include/private/pixelflinger/ |
| ggl_fixed.h | 215 "sltu %[tmp1],%[tmp1],%[tmp]\t\n" /*obit*/
231 "sltu %[tmp1],%[tmp1],%[tmp] \t\n" /*obit?*/
248 "sltu %[tmp1],%[tmp1],%[tmp] \t\n" /*obit?*/
271 "sltu %[tmp1],%[tmp1],%[tmp] \t\n" /*obit?*/
|
| /external/chromium_org/v8/src/mips/ |
| macro-assembler-mips.cc | 730 void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
732 sltu(rd, rs, rt.rm());
740 sltu(rd, rs, at);
[all...] |
| constants-mips.cc | 268 case SLTU:
|
| deoptimizer-mips.cc | 84 // sltu at, sp, t0 / slt at, a3, zero_reg (in case of count based interrupts)
111 // Replace the sltu instruction with load-imm 1 to at, so beq is not taken.
133 // Restore the sltu instruction so beq can be taken again.
|
| disasm-mips.cc | 730 case SLTU:
731 Format(instr, "sltu 'rd, 'rs, 'rt");
|
| constants-mips.h | 340 SLTU = ((5 << 3) + 3),
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 730 void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
732 sltu(rd, rs, rt.rm());
740 sltu(rd, rs, at);
[all...] |
| constants-mips.cc | 264 case SLTU:
|
| deoptimizer-mips.cc | 122 // sltu at, sp, t0 / slt at, a3, zero_reg (in case of count based interrupts)
132 // Replace the sltu instruction with load-imm 1 to at, so beq is not taken.
168 // Restore the sltu instruction so beq can be taken again.
173 patcher.masm()->sltu(at, sp, t0);
[all...] |
| disasm-mips.cc | 717 case SLTU:
718 Format(instr, "sltu 'rd, 'rs, 'rt");
|
| /external/llvm/test/CodeGen/Mips/ |
| selpat.ll | 286 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
311 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
336 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| /art/runtime/ |
| disassembler_mips.cc | 86 { kRTypeMask, 43, "sltu", "DST", },
|
| /frameworks/native/opengl/libagl/ |
| matrix.h | 90 "sltu %[t3],%[t1],%[res]\r\n"
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 264 void Sltu(Register rd, Register rs, Register rt);
|
| /bionic/libc/arch-mips/string/ |
| memcpy.S | 76 sltu AT,t0,a2
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 371 # CHECK: sltu $3, $3, $5
|
| mips32_le.txt | 377 # CHECK: sltu $3, $3, $5
|
| mips32r2.txt | 374 # CHECK: sltu $3, $3, $5
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| mips32r2_le.txt | 374 # CHECK: sltu $3, $3, $5
|
| /art/compiler/dex/quick/mips/ |
| mips_lir.h | 360 kMipsSltu, // sltu d,s,t [000000] s[25..21] t[20..16] d[15..11] [00000101011].
|
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 453 kMipsSltu, /* sltu d,s,t [000000] s[25..21] t[20..16] d[15..11] [00000101011] */
|
