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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/
svga_resource_buffer.h 187 assert(((struct svga_buffer *)buffer)->b.vtbl == &svga_buffer_vtbl);
svga_resource_texture.c 415 tex->b.vtbl = &svga_texture_vtbl;
539 tex->b.vtbl = &svga_texture_vtbl;
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_vs_surface_state.c 98 intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0,
gen7_wm_surface_state.c 599 intel->vtbl.update_texture_surface = gen7_update_texture_surface;
600 intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
601 intel->vtbl.update_null_renderbuffer_surface =
603 intel->vtbl.create_constant_surface = gen7_create_constant_surface;
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_fbo.c 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp);
281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset,
442 ok = rmesa->vtbl.blit(ctx, rrb->map_bo, 0,
937 if (!radeon->vtbl.is_format_renderable(mesa_format)){
radeon_queryobj.c 144 radeon->vtbl.emit_query_finish(radeon);
radeon_common_context.c 240 if (radeon->vtbl.free_context)
241 radeon->vtbl.free_context(radeon->glCtx);
  /external/mesa3d/src/gallium/auxiliary/pipebuffer/
pb_bufmgr_mm.c 200 mm_buf->base.vtbl = &mm_buffer_vtbl;
pb_bufmgr_pool.c 304 pool_buf->base.vtbl = &pool_buffer_vtbl;
  /external/mesa3d/src/gallium/drivers/r300/
r300_screen_buffer.c 156 rbuf->b.vtbl = &r300_buffer_vtbl;
  /external/mesa3d/src/gallium/drivers/radeonsi/
r600_buffer.c 172 rbuffer->b.vtbl = &r600_buffer_vtbl;
  /external/mesa3d/src/gallium/drivers/svga/
svga_resource_buffer.h 187 assert(((struct svga_buffer *)buffer)->b.vtbl == &svga_buffer_vtbl);
svga_resource_texture.c 415 tex->b.vtbl = &svga_texture_vtbl;
539 tex->b.vtbl = &svga_texture_vtbl;
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_vs_surface_state.c 98 intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0,
gen7_wm_surface_state.c 599 intel->vtbl.update_texture_surface = gen7_update_texture_surface;
600 intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
601 intel->vtbl.update_null_renderbuffer_surface =
603 intel->vtbl.create_constant_surface = gen7_create_constant_surface;
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_fbo.c 259 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp);
281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset,
442 ok = rmesa->vtbl.blit(ctx, rrb->map_bo, 0,
937 if (!radeon->vtbl.is_format_renderable(mesa_format)){
radeon_queryobj.c 144 radeon->vtbl.emit_query_finish(radeon);
radeon_common_context.c 240 if (radeon->vtbl.free_context)
241 radeon->vtbl.free_context(radeon->glCtx);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nouveau/
nouveau_buffer.c 365 buffer->vtbl = &nouveau_buffer_vtbl;
417 buffer->vtbl = &nouveau_buffer_vtbl;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv30/
nv30_miptree.c 298 mt->base.vtbl = &nv30_miptree_vtbl;
384 mt->base.vtbl = &nv30_miptree_vtbl;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/
nv50_miptree.c 267 mt->base.vtbl = &nv50_miptree_vtbl;
333 mt->base.vtbl = &nv50_miptree_vtbl;
  /external/llvm/include/llvm/IR/
IntrinsicsARM.td 133 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
134 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
  /external/mesa3d/src/gallium/drivers/nouveau/
nouveau_buffer.c 365 buffer->vtbl = &nouveau_buffer_vtbl;
417 buffer->vtbl = &nouveau_buffer_vtbl;
  /external/mesa3d/src/gallium/drivers/nv30/
nv30_miptree.c 298 mt->base.vtbl = &nv30_miptree_vtbl;
384 mt->base.vtbl = &nv30_miptree_vtbl;
  /external/mesa3d/src/gallium/drivers/nv50/
nv50_miptree.c 267 mt->base.vtbl = &nv50_miptree_vtbl;
333 mt->base.vtbl = &nv50_miptree_vtbl;

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