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/external/llvm/test/CodeGen/X86/
live-out-reg-info.ll	1 ; RUN: llc < %s -march=x86-64 | grep testb
longlong-deadload.ll	1 ; RUN: llc < %s -march=x86 | FileCheck %s
neg_fp.ll	1 ; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
nonconst-static-ev.ll	1 ; RUN: not llc -march=x86 -mtriple=x86_64-linux-gnu < %s 2> %t
peep-vector-extract-insert.ll	1 ; RUN: llc < %s -march=x86-64 | grep "xorps %xmm0, %xmm0" | count 2
pr10524.ll	1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41
pr10525.ll	1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41
pr10526.ll	1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41
pr11998.ll	1 ; RUN: llc < %s -mcpu=corei7-avx -march=x86-64 -mattr=+avx
pr14562.ll	1 ; RUN: llc < %s -march=x86 | FileCheck %s
pr3250.ll	1 ; RUN: llc < %s -march=x86
pr7882.ll	1 ; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin -pre-RA-sched=fast \
promote-i16.ll	1 ; RUN: llc < %s -march=x86 | FileCheck %s
rdrand.ll	2 declare {i16, i32} @llvm.x86.rdrand.16() 3 declare {i32, i32} @llvm.x86.rdrand.32() 4 declare {i64, i32} @llvm.x86.rdrand.64() 7 %call = call {i16, i32} @llvm.x86.rdrand.16() 22 %call = call {i32, i32} @llvm.x86.rdrand.32() 36 %call = call {i64, i32} @llvm.x86.rdrand.64() 51 %rand1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind 53 %rand2 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind 73 %rand = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
rem.ll	1 ; RUN: llc < %s -march=x86 | not grep div
scalar-extract.ll	1 ; RUN: llc < %s -march=x86 -mattr=+mmx -o %t
scalar_sse_minmax.ll	1 ; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \ 3 ; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \ 40 %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1] 44 declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
sdiv-exact.ll	1 ; RUN: llc -march=x86 < %s | FileCheck %s
sext-ret-val.ll	1 ; RUN: llc < %s -march=x86 | grep movzbl | count 1
shift-combine.ll	1 ; RUN: llc -march=x86 < %s | FileCheck %s
shl_elim.ll	1 ; RUN: llc < %s -march=x86 | FileCheck %s
split-vector-bitcast.ll	1 ; RUN: llc < %s -march=x86 -mattr=-sse2,+sse | grep addps
sse-fcopysign.ll	1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep test
sse2-mul.ll	1 ; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s
sse_partial_update.ll	13 %0 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a) nounwind 22 declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone 28 %0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind 36 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone

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