| /external/llvm/include/llvm/ADT/ |
| BitVector.h | 181 // Mask off previous bits.
257 BitWord Mask = EMask - IMask;
258 Bits[I / BITWORD_SIZE] |= Mask;
295 BitWord Mask = EMask - IMask;
296 Bits[I / BITWORD_SIZE] &= ~Mask;
333 BitWord Mask = 1L << (Idx % BITWORD_SIZE);
334 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
484 // Portable bit mask operations.
492 // bit mask is always a whole multiple of 32 bits. If no bit mask size i
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 92 int64_t Mask = 0xffff;
94 Offset = OldOffset & Mask;
96 Mask >>= 1;
97 assert(Mask && "One offset must be OK");
|
| /external/chromium_org/tools/gyp/tools/ |
| pretty_gyp.py | 29 """Mask the quoted strings so we skip braces inside quoted strings."""
42 """Mask the quoted strings so we skip braces inside quoted strings."""
|
| /external/clang/include/clang/AST/ |
| Type.h | 155 /// The width of the "fast" qualifier mask.
158 /// The fast qualifier mask.
162 Qualifiers() : Mask(0) {}
168 if (!(L.Mask & ~CVRMask) && !(R.Mask & ~CVRMask)) {
170 Q.Mask = L.Mask & R.Mask;
171 L.Mask &= ~Q.Mask;
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 87 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
88 unsigned Offset = countTrailingZeros(Mask);
92 Mask >>= Offset;
145 // Mask out the reserved registers
186 // The bit mask contains all register classes that are projected into B
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 194 unsigned Mask = 0, Pos = 3;
208 Mask |= (NCC & 1) << Pos;
228 // Finalize IT mask.
229 Mask |= (1 << Pos);
230 // Tag along (firstcond[0] << 4) with the mask.
231 Mask |= (CC & 1) << 4;
232 MIB.addImm(Mask);
|
| Thumb1RegisterInfo.cpp | 384 unsigned Mask = (1 << NumBits) - 1;
385 if (((Offset / Scale) & ~Mask) == 0) {
418 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
421 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
423 Offset = (Offset - Mask * Scale);
453 unsigned Mask = (1 << NumBits) - 1;
455 if ((unsigned)Offset <= Mask * Scale) {
470 Mask = (1 << NumBits) - 1;
478 ImmedOffset = ImmedOffset & Mask;
480 Offset &= ~(Mask * Scale)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 76 uint32_t Mask = (1u << 4);
81 Mask |= Bit;
84 // Emit this opcode when the mask covers every registers.
85 uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
|
| ARMELFStreamer.cpp | 469 uint32_t Mask = 0;
475 if ((Mask & Bit) == 0) {
476 Mask |= Bit;
490 UnwindOpAsm.EmitVFPRegSave(Mask);
492 UnwindOpAsm.EmitRegSave(Mask);
|
| /external/llvm/lib/IR/ |
| ConstantFold.h | 41 Constant *Mask);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 34 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
| MipsSEISelDAGToDAG.cpp | 47 unsigned Mask = MI.getOperand(1).getImm();
50 if (Mask & 1)
53 if (Mask & 2)
56 if (Mask & 4)
59 if (Mask & 8)
62 if (Mask & 16)
65 if (Mask & 32)
|
| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 179 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
187 if (Mask) {
271 bool Mask = false;
277 // Mask the write if the original instruction does not write to
279 Mask = (Chan != TRI.getHWRegChan(DstReg));
305 if (Mask) {
|
| /external/chromium_org/third_party/openssl/openssl/crypto/asn1/ |
| charmap.pl | 68 * Mask of various character properties
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 138 uint64_t Mask = ((uint64_t)(-1) >>
140 CurVal |= Value & Mask;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 207 int &Mask, int &Value) const;
211 int Mask, int Value,
|
| /external/openssl/crypto/asn1/ |
| charmap.pl | 68 * Mask of various character properties
|
| /external/libnfc-nxp/src/ |
| phFriNfc_NdefRecord.h | 115 #define PH_FRINFC_NDEFRECORD_FLAG_MASK ((uint8_t)0xF8) /** \internal To Mask the Flag Byte */
450 static uint8_t phFriNfc_NdefRecord_NdefFlag(uint8_t Flags,uint8_t Mask);
|
| /external/llvm/include/llvm/Analysis/ |
| ValueTracking.h | 29 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
31 /// bit sets. This code only analyzes bits in Mask, in order to short-circuit
36 /// where V is a vector, the mask, known zero, and known one values are the
61 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
62 /// this predicate to simplify operations downstream. Mask is known to be
67 /// where V is a vector, the mask, known zero, and known one values are the
70 bool MaskedValueIsZero(Value *V, const APInt &Mask,
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 346 /// physical registers. The individual bits in a lane mask can't be assigned
362 // SubIdx == 0 is allowed, it has the lane mask ~0u.
381 /// This function returns a bit mask of lanes that completely cover their
426 /// getCallPreservedMask - Return a mask of call-preserved registers for the
427 /// given calling convention on the current sub-target. The mask should
431 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
433 /// preserved across the function call. The bit mask is expected to be
438 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
440 /// A NULL pointer means that no register mask will be used, and call
445 // The default mask clobbers everything. All targets should override
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/extensions/ |
| security.h | 187 Mask access_mode);
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/extensions/ |
| security.h | 187 Mask access_mode);
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/extensions/ |
| security.h | 187 Mask access_mode);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 395 // Instead, we load all significant words, mask bits off, and concatenate
579 SDValue Mask = Op.getOperand(0);
583 assert(VT.isVector() && !Mask.getValueType().isVector()
599 // Generate a mask operand.
603 && "Invalid mask size");
605 // What is the size of each element in the vector mask.
608 Mask = DAG.getSelect(DL, BitTy, Mask,
612 // Broadcast the mask so that the entire vector is all-one or all zero.
613 SmallVector<SDValue, 8> Ops(NumElem, Mask);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
