| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 234 APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits));
236 ConstantInt::get(BO->getContext(), Mask));
274 APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits));
276 ConstantInt::get(BO->getContext(), Mask));
382 // The mask we constructed says what the trunc would do if occurring
385 // mask as appropriate.
440 V1->getName()+".mask");
470 V1->getName()+".mask");
570 APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt1));
572 ConstantInt::get(I.getContext(), Mask));
[all...] |
| InstCombine.h | 237 Value *EvaluateInDifferentElementOrder(Value *V, ArrayRef<int> Mask);
307 bool MaskedValueIsZero(Value *V, const APInt &Mask,
309 return llvm::MaskedValueIsZero(V, Mask, TD, Depth);
369 Value *FoldLogicalPlusAnd(Value *LHS, Value *RHS, ConstantInt *Mask,
|
| InstCombineCalls.cpp | 325 APInt Mask(APInt::getLowBitsSet(BitWidth, TrailingZeros));
326 if ((Mask & KnownZero) == Mask)
343 APInt Mask(APInt::getHighBitsSet(BitWidth, LeadingZeros));
344 if ((Mask & KnownZero) == Mask)
580 // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
581 if (Constant *Mask = dyn_cast<Constant>(II->getArgOperand(2)))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | 89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
90 unsigned Mask;
100 LiveBundle() : Mask(0), FixCount(0) {}
103 bool isFixed() const { return !Mask || FixCount; }
115 unsigned Mask = 0;
121 Mask |= 1 << (Reg - X86::FP0);
123 return Mask;
296 /// Adjust the live registers to be the set in Mask.
297 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
397 const unsigned Mask = calcLiveInMask(MBB)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 81 unsigned Mask = MBBI->getOperand(1).getImm();
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
573 unsigned Mask = (1 << NumBits) - 1;
574 if ((unsigned)Offset <= Mask * Scale) {
590 ImmedOffset = ImmedOffset & Mask;
603 Offset &= ~(Mask*Scale);
|
| /external/chromium_org/third_party/leveldatabase/src/db/ |
| log_writer.cc | 87 crc = crc32c::Mask(crc); // Adjust for storage
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.h | 176 unsigned char Mask;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| dxbc_parse.cpp | 82 param.Mask = sig->elements[i].mask;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| gen6_depthstencil.c | 88 ds->ds2.depth_write_enable = ctx->Depth.Mask;
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.h | 176 unsigned char Mask;
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| dxbc_parse.cpp | 82 param.Mask = sig->elements[i].mask;
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen6_depthstencil.c | 88 ds->ds2.depth_write_enable = ctx->Depth.Mask;
|
| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | 345 std::vector<Constant*> &Mask);
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 94 APInt Mask = APInt::getLowBitsSet(BitWidth, LHSKnownZeroOut);
95 KnownZero |= KnownZero2 & Mask;
96 KnownOne |= KnownOne2 & Mask;
105 APInt Mask = APInt::getLowBitsSet(BitWidth, RHSKnownZeroOut);
106 KnownZero |= LHSKnownZero & Mask;
107 KnownOne |= LHSKnownOne & Mask;
243 "V, Mask, KnownOne and KnownZero should have same BitWidth");
[all...] |
| /external/clang/lib/Driver/ |
| SanitizerArgs.h | 184 /// provides a sanitizer kind in \p Mask. For example, the argument list
185 /// "-fsanitize=thread,vptr -faddress-sanitizer" with mask \c NeedsUbsanRt
203 /// a value in \p Mask. For instance, the argument
204 /// "-fsanitize=address,alignment" with mask \c NeedsUbsanRt would produce
208 unsigned Mask) {
213 if (parse(A->getValue(I)) & Mask)
|
| /external/llvm/lib/Target/R600/ |
| R600TextureIntrinsicsReplacer.cpp | 126 Constant *Mask[] = {
132 Value *SwizzleMask = ConstantVector::get(Mask);
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/ |
| X.h | 75 typedef unsigned long Mask;
91 typedef CARD32 Mask;
152 /* Input Event Masks. Used as event-mask window attribute and as arguments
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| X.h | 75 typedef unsigned long Mask;
91 typedef CARD32 Mask;
152 /* Input Event Masks. Used as event-mask window attribute and as arguments
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| X.h | 75 typedef unsigned long Mask;
91 typedef CARD32 Mask;
152 /* Input Event Masks. Used as event-mask window attribute and as arguments
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 776 unsigned Mask = Op.getImm() & 0xf;
781 // For reads of the special registers ignore the "mask encoding" bits
786 default: llvm_unreachable("Unexpected mask value!");
828 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
830 switch (Mask) {
831 default: llvm_unreachable("Unexpected mask value!");
843 if (Mask) {
845 if (Mask & 8) O << 'f'
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 951 // Because there are S+1 ones in the replicated mask, an immediate of all
961 // First we have to make sure the mask is actually repeated in each slot for
1055 uint64_t Mask = (1ULL << Num1s) - 1;
1058 Mask = (Mask >> Rotation)
1059 | ((Mask << (Width - Rotation)) & WidthMask);
1061 Imm = Mask;
1063 Mask <<= Width;
1064 Imm |= Mask;
1076 // If the value is 0 when we mask out all the bits that could be set wit
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 26 // Return a mask with Count low bits set.
780 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
783 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
784 unsigned First = findFirstSet(Mask);
785 uint64_t Top = (Mask >> First) + 1;
794 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
797 if (Mask == 0)
803 if (isStringOfOnes(Mask, LSB, Length)) {
811 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 58 MO_RegisterMask, ///< Mask of preserved registers.
458 /// It is sometimes necessary to detach the register mask pointer from its
460 /// mask pointers.
472 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
642 /// CreateRegMask - Creates a register mask operand referencing Mask. The
643 /// operand does not take ownership of the memory referenced by Mask, it must
648 /// mask has a bit set for each physreg that is preserved by this
652 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
654 static MachineOperand CreateRegMask(const uint32_t *Mask) {
[all...] |
| /external/llvm/include/llvm/Support/ |
| MathExtras.h | 59 T Mask = std::numeric_limits<T>::max() >> Shift;
61 if ((Val & Mask) == 0) {
66 Mask >>= Shift;
|
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 270 /// in Mask.
272 BitVector Mask(TRI->getNumRegs());
276 Mask.set(*I);
277 return Mask;
|
